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top252-262 topswitch-hx family www.powerint.com june 2013 enhanced ecosmart ? , integrated off-line switcher with advanced feature set and extended power range ? product highlights lower system cost, higher design flexibility ? multi-mode operation maximizes effciency at all loads ? new esip-7f and esip-7c packages ? low thermal impedance junction-to-case (2 c per watt) ? low height is ideal for adapters where space is limited ? simple mounting using a clip to aid low cost manufacturing ? horizontal esip-7f package ideal for ultra low height adapter and monitor applications ? extended package creepage distance from drain pin to adjacent pin and to heat sink ? no heat sink required up to 35 w using p, g and m packages with universal input voltage and up to 48 w at 230 vac ? output overvoltage protection (ovp) is user programmable for latching/non-latching shutdown with fast ac reset ? allows both primary and secondary sensing ? line undervoltage (uv) detection prevents turn-off glitches ? line overvoltage (ov) shutdown extends line surge limit ? accurate programmable current limit ? optimized line feed-forward for line ripple rejection ? 132 khz frequency (254y-258y and all e/l packages) reduces transformer and power supply size ? half frequency option for video applications ? frequency jittering reduces emi flter cost figure 1. typical flyback application. ? heat sink is connected to source for low emi ? improved auto-restart delivers <3% of maximum power in short circuit and open loop fault conditions ? accurate hysteretic thermal shutdown function automatically recovers without requiring a reset ? fully integrated soft-start for minimum start-up stress ? extended creepage between drain and all other pins improves feld reliability pi-4510-100206 ac in dc out d s c t opswitch-hx control v + - f x output power table product 5 230 vac 15% 4 85-265 vac adapter 1 open frame 2 peak 3 adapter 1 open frame 2 peak 3 top252pn/gn 9 w 15 w 21 w 6 w 10 w 13 w top252mn 21 w 13 w top253pn/gn 15 w 25 w 38 w 9 w 15 w 25 w top253mn 43 w 29 w top254pn/gn 16 w 28 w 47 w 11 w 20 w 30 w top254mn 62 w 40 w top255pn/gn 19 w 30 w 54 w 13 w 22 w 35 w top255mn 81 w 52 w top256pn/gn 21 w 34 w 63 w 15 w 26 w 40 w top256mn 98 w 64 w top257pn/gn 25 w 41 w 70 w 19 w 30 w 45 w top257mn 119 w 78 w top258pn/gn 29 w 48 w 77 w 22 w 35 w 50 w top258mn 140 w 92 w table 1. output power table. (for notes see page 2). product 5 230 vac 15% 85-265 vac adapter 1 open frame 2 adapter 1 open frame 2 top252en/eg 10 w 21 w 6 w 13 w top253en/eg 21 w 43 w 13 w 29 w top254en/yn/eg 30 w 62 w 20 w 43 w top255en/yn/eg 40 w 81 w 26 w 57 w top255ln 40 w 81 w 26 w 57 w top256en/yn/eg 60 w 119 w 40 w 86 w top256ln 60 w 88 w 40 w 64 w top257en/yn/eg 85 w 157 w 55 w 119 w top257ln 85 w 105 w 55 w 78 w top258en/yn/eg 105 w 195 w 70 w 148 w top258ln 105 w 122 w 70 w 92 w top259en/yn/eg 128 w 238 w 80 w 171 w top259ln 128 w 162 w 80 w 120 w top260en/yn/eg 147 w 275 w 93 w 200 w top260ln 147 w 190 w 93 w 140 w top261en/yn/eg 177 w 333 w 118 w 254 w top261ln 177 w 244 w 118 w 177 w top262en 6 177 w 333 w 118 w 254 w top262ln 6 177 w 244 w 118 w 177 w
rev. h 06/13 2 top252-262 www.powerint.com ecosmart ? C energy effcient ? energy effcient over entire load range ? no-load consumption ? less than 200 mw at 230 vac ? standby power for 1 w input ? >600 mw output at 110 vac input ? >500 mw output at 265 vac input description topswitch-hx cost effectively incorporates a 700 v power mosfet, high voltage switched current source, pwm control, oscillator, thermal shutdown circuit, fault protection and other control circuitry onto a monolithic device. pi-4973-122607 ac in dc out d s c t opswitch-hx control v + - g x figure 2. typical flyback application top259yn, top260yn and top261yn. y package option for top259-261 in order to improve noise-immunity on large topswitch-hx y package parts, the f pin has been removed (top259-261yn are fxed at 66 khz switching frequency) and replaced with a signal ground (g) pin. this pin acts as a low noise path for the c pin capacitor and the x pin resistor. it is only required for the top259-261yn package parts. notes for table 1: 1. minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 c ambient. use of an external heat sink will increase power capability. 2. minimum continuous power in an open frame design at +50 c ambient. 3. peak power capability in any design at +50 c ambient. 4. 230 vac or 110/115 vac with doubler. 5. packages: p: dip-8c, g: smd-8c, m: sdip-10c, y: to-220-7c, e: esip-7c, l: esip-7f. see part ordering information. 6. top261 and top262 have the same current limit set point. in some applications top262 may run cooler than top261 due to a lower r ds(on) for the larger device.
rev. h 06/13 3 top252-262 www.powerint.com section list functional block diagram ....................................................................................................................................... 4 pin functional description ...................................................................................................................................... 6 topswitch-hx family functional description ....................................................................................................... 7 control (c) pin operation .................................................................................................................................... 8 oscillator and switching frequency .......................................................................................................................... 8 pulse width modulator ............................................................................................................................................ 9 maximum load cycle .............................................................................................................................................. 9 error amplifer .......................................................................................................................................................... 9 on-chip current limit with external programmability ............................................................................................... 9 line undervoltage detection (uv) ........................................................................................................................... 10 line overvoltage shutdown (ov) ............................................................................................................................ 11 hysteretic or latching output overvoltage protection (ovp) ................................................................................... 11 line feed-forward with dc max reduction .............................................................................................................. 13 remote on/off and synchronization .................................................................................................................... 13 soft-start ............................................................................................................................................................... 13 shutdown/auto-restart ......................................................................................................................................... 13 hysteretic over-temperature protection ................................................................................................................. 13 bandgap reference ............................................................................................................................................... 13 high-voltage bias current source .......................................................................................................................... 13 typical uses of frequency (f) pin ...................................................................................................................... 15 typical uses of voltage monitor (v) and external current limit (x) pins .......................................... 16 typical uses of multi-function (m) pin ........................................................................................................... 18 application examples .............................................................................................................................................. 21 a high effciency, 35 w, dual output C universal input power supply ..................................................................... 21 a high effciency, 150 w, 250-380 vdc input power supply .................................................................................. 22 a high effciency, 20 w continuous C 80 w peak, universal input power supply ................................................... 23 a high effciency, 65 w, universal input power supply ........................................................................................... 24 key application considerations .............................................................................................................................. 25 topswitch-hx vs.topswitch-gx ....................................................................................................................... . 25 topswitch-hx design considerations .................................................................................................................. 26 topswitch-hx layout considerations ................................................................................................................... 27 quick design checklist .......................................................................................................................................... 31 design tools .......................................................................................................................................................... 31 product specifcations and test conditions .......................................................................................................... 32 typical performance characteristics .................................................................................................................... 39 package outlines .................................................................................................................................................... 43 part ordering information ........................................................................................................................................ 47
rev. h 06/13 4 top252-262 www.powerint.com figure 3a. functional block diagram (p and g packages). figure 3b. functional block diagram (m package). pi-4643-082907 shutdown/ aut o-rest art clock controlled turn-on ga te driver current limit comp ara to r internal uv comp ara to r internal suppl y 5.8 v 4.8 v source (s) source (s) s r q d max st op soft st art control (c) vol t age monit or (v) - + 5.8 v i fb 1 v z c v c + - + - + - leading edge blanking 16 1 hysteretic thermal shutdown shunt regula t or/ error amplifier + - drain (d) on/off dc max dc max 0 ov/ uv ovp v v i (limit) current limit adjust v bg + v t line sense soft st art off f reduction f reduction st op logic external current limit (x) oscilla t or with jitter pwm k ps(upper) k ps(lower) soft st art i fb i ps(upper) i ps(lower) k ps(upper) k ps(lower) pi-4508-120307 shutdown/ aut o-rest art clock controlled turn-on ga te driver current limit comp ara to r internal uv comp ara to r internal suppl y 5.8 v 4.8 v k ps(upper) k ps(lower) source (s) source (s) s r q d max st op soft st art control (c) mul ti- function (m) - + 5.8 v i fb z c v c + - + - + - leading edge blanking 16 1 hysteretic thermal shutdown shunt regula t or/ error amplifier + - drain (d) on/off dc max dc max 0 ov/ uv ovp v v i (limit) current limit adjust v bg + v t line sense soft st art soft st art i fb i ps(upper) i ps(lower) k ps(upper) k ps(lower) off f reduction f reduction st op logic oscilla t or with jitter pwm
rev. h 06/13 5 top252-262 www.powerint.com figure 3c. functional block diagram (top254-258 yn package and all esip packages). pi-4511-082907 shutdown/ aut o-rest art clock controlled turn-on ga te driver current limit comp ara to r internal uv comp ara to r internal suppl y 5.8 v 4.8 v source (s) source (s) s r q d max st op soft st art control (c) vol t age monit or (v) frequency (f) - + 5.8 v i fb 1 v z c v c + - + - + - leading edge blanking 16 1 hysteretic thermal shutdown shunt regula t or/ error amplifier + - drain (d) on/off dc max dc max 66k/132k 0 ov/ uv ovp v v i (limit) current limit adjust v bg + v t line sense soft st art off f reduction f reduction st op logic external current limit (x) oscilla t or with jitter pwm k ps(upper) k ps(lower) soft st art i fb i ps(upper) i ps(lower) k ps(upper) k ps(lower) pi-4974-122607 shutdown/ aut o-rest art clock controlled turn-on ga te driver current limit comp ara to r internal uv comp ara to r internal suppl y 5.8 v 4.8 v signal ground (g) source (s) s r q d max st op soft st art control (c) vol t age monit or (v) - + 5.8 v i fb 1 v z c v c + - + - + - leading edge blanking 16 1 hysteretic thermal shutdown shunt regula t or/ error amplifier + - drain (d) source (s ) on/off dc max dc max 0 ov/ uv ovp v v i (limit) current limit adjust v bg + v t line sense soft st art off f reduction f reduction st op logic external current limit (x) oscilla t or with jitter pwm k ps(upper) k ps(lower) soft st art i fb i ps(upper) i ps(lower) k ps(upper) k ps(lower) figure 3d. functional block diagram top259yn, top260yn, top261yn.
rev. h 06/13 6 top252-262 www.powerint.com pin functional description drain (d) pin: high-voltage power mosfet drain pin. the internal start-up bias current is drawn from this pin through a switched high- voltage current source. internal current limit sense point for drain current. control (c) pin: error amplifer and feedback current input pin for duty cycle control. internal shunt regulator connection to provide internal bias current during normal operation. it is also used as the connection point for the supply bypass and auto-restart/ compensation capacitor. external current limit (x) pin (y, m, e and l package): input pin for external current limit adjustment and remote on/off. a connection to source pin disables all functions on this pin. figure 4. pin confguration (top view). x pi-4711-021308 dc input voltage + - d s c control v r il r ls 12 k? 4 m? v uv = i uv r ls + v v (i v = i uv ) v ov = i ov r ls + v v (i v = i ov ) for r ls = 4 m? dc max @100 vdc = 76% dc max @375 vd c = 41% for r il = 12 k? i limit = 61% see figure 55b for other resistor values (r il ) to select different i limit values. v uv = 102.8 vdc v ov = 451 vdc figure 5. top254-258 y and all m/e/l package line sense and externally set current limit. pi-4712-120307 dc input voltage + - d m s c v uv = i uv r ls + v m (i m = i uv ) v ov = i ov r ls + v m (i m = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @100 vdc = 76% dc max @375 vdc = 41% control r ls 4 m? figure 7. p/g package line sense. x g pi-4983-021308 dc input voltage + - d s c control v r il r ls 12 k? 4 m? v uv = i uv r ls + v v (i v = i uv ) v ov = i ov r ls + v v (i v = i ov ) for r ls = 4 m? dc max @100 vdc = 76% dc max @375 vd c = 41% for r il = 12 k? i limit = 61% see figure 55b for other resistor values (r il ) to select different i limit values. v uv = 102.8 vdc v ov = 451 vdc figure 6. top259-261 y package line sense and external current limit. voltage monitor (v) pin (y & m package only): input for ov, uv, line feed forward with dc max reduction, output overvoltage protection (ovp), remote on/off and device reset. a connection to the source pin disables all functions on this pin. multi-function (m) pin (p & g packages only): this pin combines the functions of the voltage monitor (v) and external current limit (x) pins of the y package into one pin. input pin for ov, uv, line feed forward with dc max pi-4644-091108 t ab internally connected to source pin ta b internally connected to source pin lead bend outward from drawing (refer to esip-7f package outline drawing) exposed pad (hidden) internally connected to source pin y package (t o-220-7c) d c s s s s s s s s s 7 d 5 f 4 s 3 c 2 x 1 v 7 d 5 s 4 f 3 c 2 x 1 v 7 d 5 s 4 f 3 c 2 x 1 v 7 d 5 g 4 s 3 c 2 x 1 v m p and g package m package 8 5 7 1 4 2 6 d x c v 10 6 9 1 5 8 7 2 3 note: y package for top259-261 note: y package for top254-258 e package (esip-7c) l package (esip-7f) y package (t o-220-7c)
rev. h 06/13 7 top252-262 www.powerint.com pi-4713-021308 dc input voltage + - d m s c for r il = 12 k? i limit = 61% control r il see figure 55b for other resistor values (r il ) to select different i limit values. for r il = 19 k? i limit = 37% figure 8. p/g package externally set current limit. reduction, output overvoltage protection (ovp), external current limit adjustment, remote on/off and device reset. a connection to source pin disables all functions on this pin and makes topswitch-hx operate in simple three terminal mode (like topswitch-ii). frequency (f) pin (top254-258y, and all e and l packages): input pin for selecting switching frequency 132 khz if connected to source pin and 66 khz if connected to control pin. the switching frequency is internally set for fxed 66 khz operation in the p, g, m package and top259yn, top260yn and top261yn. signal ground (g) pin (top259yn, top260yn & top261yn only): return for c pin capacitor and x pin resistor. source (s) pin: output mosfet source connection for high voltage power return. primary side control circuit common and reference point. topswitch-hx family functional description like topswitch-gx, topswitch-hx is an integrated switched mode power supply chip that converts a current at the control input to a duty cycle at the open drain output of a high voltage power mosfet. during normal operation the duty cycle of the power mosfet decreases linearly with increasing control pin current as shown in figure 9. in addition to the three terminal topswitch features, such as the high voltage start-up, the cycle-by-cycle current limiting, loop compensation circuitry, auto-restart and thermal shutdown, the topswitch-hx incorporates many additional functions that reduce system cost, increase power supply performance and design fexibility. a patented high voltage cmos technology allows both the high-voltage power mosfet and all the low voltage control circuitry to be cost effectively integrated onto a single monolithic chip. three terminals, frequency, voltage-monitor, and external current limit (available in y and e/l packages), two terminals, voltage-monitor and external current limit (available in m package) or one terminal multi-function (available in p and g package) have been used to implement some of the new functions. these terminals can be connected to the source pin to operate the topswitch-hx in a topswitch-like three terminal mode. however, even in this three terminal mode, the topswitch-hx offers many transparent features that do not require any external components: 1. a fully integrated 17 ms soft-start signifcantly reduces or eliminates output overshoot in most applications by sweeping both current limit and frequency from low to high to limit the peak currents and voltages during start-up. 2. a maximum duty cycle (dc max ) of 78% allows smaller input storage capacitor, lower input voltage requirement and/or higher power capability. 3. multi-mode operation optimizes and improves the power supply effciency over the entire load range while maintaining good cross regulation in multi-output supplies. figure 9. control pin characteristics (multi-mode operation). pi-4645-041107 duty cycle (%) drain peak current to current limit ratio (%) frequency (khz) control current control current control current i coff i c03 i c02 i c01 i b i cd1 100 78 55 25 132 66 30 slope = pwm gain (constant over load range) auto-restart va riable frequency mode low frequency mode multi-cycle modulation jitter full frequency mode
rev. h 06/13 8 top252-262 www.powerint.com 4. switching frequency of 132 khz reduces the transformer size with no noticeable impact on emi. 5. frequency jittering reduces emi in the full frequency mode at high load condition. 6. hysteretic over-temperature shutdown ensures automatic recovery from thermal fault. large hysteresis prevents circuit board overheating. 7. packages with omitted pins and lead forming provide large drain creepage distance. 8. reduction of the auto-restart duty cycle and frequency to improve the protection of the power supply and load during open loop fault, short circuit, or loss of regulation. 9. tighter tolerances on i 2 f power coeffcient, current limit reduction, pwm gain and thermal shutdown threshold. the voltage-monitor (v) pin is usually used for line sensing by connecting a 4 m w resistor from this pin to the rectifed dc high voltage bus to implement line overvoltage (ov), under- voltage (uv) and dual-slope line feed-forward with dc max reduction. in this mode, the value of the resistor determines the ov/uv thresholds and the dc max is reduced linearly with a dual slope to improve line ripple rejection. in addition, it also provides another threshold to implement the latched and hysteretic output overvoltage protection (ovp). the pin can also be used as a remote on/off using the i uv threshold. the external current limit (x) pin can be used to reduce the current limit externally to a value close to the operating peak current, by connecting the pin to source through a resistor. this pin can also be used as a remote on/off input. for the p and g package the voltage-monitor and external current limit pin functions are combined on one multi-function (m) pin. however, some of the functions become mutually exclusive. the frequency (f) pin in the top254-258 y and e/l packages set the switching frequency in the full frequency pwm mode to the default value of 132 khz when connected to source pin. a half frequency option of 66 khz can be chosen by connecting this pin to the control pin instead. leaving this pin open is not recommended. in the p, g and m packages and the top259-261 y packages, the frequency is set internally at 66 khz in the full frequency pwm mode. control (c) pin operation the control pin is a low impedance node that is capable of receiving a combined supply and feedback current. during normal operation, a shunt regulator is used to separate the feedback signal from the supply current. control pin voltage v c is the supply voltage for the control circuitry including the mosfet gate driver. an external bypass capacitor closely connected between the control and source pins is required to supply the instantaneous gate drive current. the total amount of capacitance connected to this pin also sets the auto-restart timing as well as control loop compensation. when rectifed dc high voltage is applied to the drain pin during start-up, the mosfet is initially off, and the control pin capacitor is charged through a switched high voltage current source connected internally between the drain and control pins. when the control pin voltage v c reaches approximately 5.8 v, the control circuitry is activated and the soft-start begins. the soft-start circuit gradually increases the drain peak current and switching frequency from a low starting value to the maximum drain peak current at the full frequency over approximately 17 ms. if no external feedback/supply current is fed into the control pin by the end of the soft-start, the high voltage current source is turned off and the control pin will start discharging in response to the supply current drawn by the control circuitry. if the power supply is designed properly, and no fault condition such as open loop or shorted output exists, the feedback loop will close, providing external control pin current, before the control pin voltage has had a chance to discharge to the lower threshold voltage of approximately 4.8 v (internal supply undervoltage lockout threshold). when the externally fed current charges the control pin to the shunt regulator voltage of 5.8 v, current in excess of the consumption of the chip is shunted to source through an nmos current mirror as shown in figure 3. the output current of that nmos current mirror controls the duty cycle of the power mosfet to provide closed loop regulation. the shunt regulator has a fnite low output impedance z c that sets the gain of the error amplifer when used in a primary feedback confguration. the dynamic impedance z c of the control pin together with the external control pin capacitance sets the dominant pole for the control loop. when a fault condition such as an open loop or shorted output prevents the fow of an external current into the control pin, the capacitor on the control pin discharges towards 4.8 v. at 4.8 v, auto-restart is activated, which turns the output mosfet off and puts the control circuitry in a low current standby mode. the high-voltage current source turns on and charges the external capacitance again. a hysteretic internal supply undervoltage comparator keeps v c within a window of typically 4.8 v to 5.8 v by turning the high-voltage current source on and off as shown in figure 11. the auto-restart circuit has a divide-by-sixteen counter, which prevents the output mosfet from turning on again until sixteen discharge/ charge cycles have elapsed. this is accomplished by enabling the output mosfet only when the divide-by-sixteen counter reaches the full count (s15). the counter effectively limits topswitch-hx power dissipation by reducing the auto-restart duty cycle to typically 2%. auto-restart mode continues until output voltage regulation is again achieved through closure of the feedback loop. oscillator and switching frequency the internal oscillator linearly charges and discharges an internal capacitance between two voltage levels to create a triangular waveform for the timing of the pulse width modulator. this oscillator sets the pulse width modulator/current limit latch at the beginning of each cycle. the nominal full switching frequency of 132 khz was chosen to minimize transformer size while keeping the fundamental emi frequency below 150 khz. the frequency pin (available only in top254-258 y and e, l packages), when shorted to the control pin, lowers the full switching frequency to 66 khz
rev. h 06/13 9 top252-262 www.powerint.com figure 10. switching frequency jitter (idealized v drain waveforms). pi-4530-041 10 7 f osc - 4 ms ti me switching frequency v drain f osc + (half frequency), which may be preferable in some cases such as noise sensitive video applications or a high effciency standby mode. otherwise, the frequency pin should be connected to the source pin for the default 132 khz. in the m, p and g packages and the top259-261 y package option, the full frequency pwm mode is set at 66 khz, for higher effciency and increased output power in all applications. to further reduce the emi level, the switching frequency in the full frequency pwm mode is jittered (frequency modulated) by approximately 2.5 khz for 66 khz operation or 5 khz for 132 khz operation at a 250 hz (typical) rate as shown in figure 10. the jitter is turned off gradually as the system is entering the variable frequency mode with a fxed peak drain current. pulse width modulator the pulse width modulator implements multi-mode control by driving the output mosfet with a duty cycle inversely proportional to the current into the control pin that is in excess of the internal supply current of the chip (see figure 9). the feedback error signal, in the form of the excess current, is fltered by an rc network with a typical corner frequency of 7 khz to reduce the effect of switching noise in the chip supply current generated by the mosfet gate driver. to optimize power supply effciency, four different control modes are implemented. at maximum load, the modulator operates in full frequency pwm mode; as load decreases, the modulator automatically transitions, frst to variable frequency pwm mode, then to low frequency pwm mode. at light load, the control operation switches from pwm control to multi-cycle- modulation control, and the modulator operates in multi-cycle- modulation mode. although different modes operate differently to make transitions between modes smooth, the simple relationship between duty cycle and excess control pin current shown in figure 9 is maintained through all three pwm modes. please see the following sections for the details of the operation of each mode and the transitions between modes. full frequency pwm mode: the pwm modulator enters full frequency pwm mode when the control pin current (i c ) reaches i b . in this mode, the average switching frequency is kept constant at f osc (66 khz for p, g and m packages and top259-261 y, pin selectable 132 khz or 66 khz for y and e/l packages). duty cycle is reduced from dc max through the reduction of the on-time when i c is increased beyond i b . this operation is identical to the pwm control of all other topswitch families. topswitch-hx only operates in this mode if the cycle-by-cycle peak drain current stays above k ps(upper) *i limit (set), where k ps(upper) is 55% (typical) and i limit (set) is the current limit externally set via the x or m pin. variable frequency pwm mode: when peak drain current is lowered to k ps(upper) * i limit (set) as a result of power supply load reduction, the pwm modulator initiates the transition to variable frequency pwm mode, and gradually turns off frequency jitter. in this mode, peak drain current is held constant at k ps(upper) * i limit (set) while switching frequency drops from the initial full frequency of f osc (132 khz or 66 khz) towards the minimum frequency of f mcm(min) (30 khz typical). duty cycle reduction is accomplished by extending the off-time. low frequency pwm mode: when switching frequency reaches f mcm(min) (30 khz typical), the pwm modulator starts to transition to low frequency mode. in this mode, switching frequency is held constant at f mcm(min) and duty cycle is reduced, similar to the full frequency pwm mode, through the reduction of the on-time. peak drain current decreases from the initial value of k ps(upper) * i limit (set) towards the minimum value of k ps(lower) *i limit (set), where k ps(lower) is 25% (typical) and i limit (set) is the current limit externally set via the x or m pin. multi-cycle-modulation mode: when peak drain current is lowered to k ps(lower) *i limit (set), the modulator transitions to multi-cycle-modulation mode. in this mode, at each turn-on, the modulator enables output switching for a period of t mcm(min) at the switching frequency of f mcm(min) (4 or 5 consecutive pulses at 30 khz) with the peak drain current of k ps(lower) *i limit (set), and stays off until the control pin current falls below i c(off) . this mode of operation not only keeps peak drain current low but also minimizes harmonic frequencies between 6 khz and 30 khz. by avoiding transformer resonant frequency this way, all potential transformer audible noises are greatly suppressed. maximum duty cycle the maximum duty cycle, dc max , is set at a default maximum value of 78% (typical). however, by connecting the voltage- monitor or multi-function pin (depending on the package) to the rectifed dc high voltage bus through a resistor with appropriate value (4 m w typical), the maximum duty cycle can be made to decrease from 78% to 40% (typical) when input line voltage increases from 88 v to 380 v, with dual gain slopes. error amplifer the shunt regulator can also perform the function of an error amplifer in primary side feedback applications. the shunt regulator voltage is accurately derived from a temperature- compensated bandgap reference. the control pin dynamic impedance z c sets the gain of the error amplifer. the control pin clamps external circuit signals to the v c voltage level. the control pin current in excess of the supply current is separated by the shunt regulator and becomes the feedback current i fb for the pulse width modulator.
rev. h 06/13 10 top252-262 www.powerint.com on-chip current limit with external programmability the cycle-by-cycle peak drain current limit circuit uses the output mosfet on-resistance as a sense resistor. a current limit comparator compares the output mosfet on-state drain to source voltage v ds(on) with a threshold voltage. high drain current causes v ds(on) to exceed the threshold voltage and turns the output mosfet off until the start of the next clock cycle. the current limit comparator threshold voltage is temperature compensated to minimize the variation of the current limit due to temperature related changes in r ds(on) of the output mosfet. the default current limit of topswitch-hx is preset internally. however, with a resistor connected between external current limit (x) pin (y, e/l and m packages) or multi- function (m) pin (p and g package) and source pin (for top259-261 y, the x pin is connected to the signal ground (g) pin), current limit can be programmed externally to a lower level between 30% and 100% of the default current limit. by setting current limit low, a larger topswitch-hx than necessary for the power required can be used to take advantage of the lower r ds(on) for higher effciency/smaller heat sinking requirements. topswitch-hx current limit reduction initial tolerance through the x pin (or m pin) has been improved signifcantly compare with previous topswitch-gx. with a second resistor connected between the external current limit (x) pin (y, e/l and m packages) or multi-function (m) pin (p and g package) and the rectifed dc high voltage bus, the current limit is reduced with increasing line voltage, allowing a true power limiting operation against line variation to be implemented. when using an rcd clamp, this power limiting technique reduces maximum clamp voltage at high line. this allows for higher refected voltage designs as well as reducing clamp dissipation. t he leading edge blanking circuit inhibits the current limit comparator for a short time after the output mosfet is turned on. the leading edge blanking time has been set so that, if a power supply is designed properly, current spikes caused by primary-side capacitances and secondary-side rectifer reverse recovery time should not cause premature termination of the switching pulse. the current limit is lower for a short period after the leading edge blanking time. this is due to dynamic characteristics of the mosfet. during startup and fault conditions the controller prevents excessive drain currents by reducing the switching frequency. line undervoltage detection (uv) a t power up, uv keeps topswitch-hx off until the input line voltage reaches the undervoltage threshold. at power down, uv prevents auto-restart attempts after the output goes out of regulation. this eliminates power down glitches caused by slow discharge of the large input storage capacitor present in applications such as standby supplies. a single resistor connected from the voltage-monitor pin (y, e/l and m packages) or multi-function pin (p and g packages) to the rectifed dc high voltage bus sets uv threshold during power up. once the power supply is successfully turned on, the uv threshold is lowered to 44% of the initial uv threshold to allow extended input voltage operating range (uv low threshold). if the uv low threshold is reached during operation without the power supply losing regulation, the device will turn off and stay off until uv (high threshold) has been reached again. if the power supply loses regulation before reaching the uv low threshold, the device will enter auto-restart. at the end of each auto-restart cycle (s15), the uv comparator is enabled. if the uv high threshold is not exceeded, the mosfet will be disabled during the next cycle (see figure 11). the uv feature can be disabled independent of the ov feature. pi-4531-121206 s13 s12 s0 s15 s13 s12 s0 s15 s14 s13 s15 s14 s14 5.8 v 4.8 v s15 0 v 0 v 0 v v line v c v drain v out note: s0 through s15 are the output states of the auto-restart counter 2 1 2 3 4 0 v ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ s0 s15 ~ ~ ~ ~ ~ ~ ~ ~ v uv ~ ~ ~ ~ ~ ~ ~ ~ s12 ~ ~ figure 11. typical waveforms for (1) power up (2) normal operation (3) auto-restart (4) power down.
rev. h 06/13 11 top252-262 www.powerint.com line overvoltage shutdown (ov) t he same resistor used for uv also sets an overvoltage threshold, which, once exceeded, will force topswitch-hx to stop switching instantaneously (after completion of the current switching cycle). if this condition lasts for at least 100 m s, the topswitch-hx output will be forced into off state. unlike with topswitch-gx, however, when the line voltage is back to normal with a small amount of hysteresis provided on the ov threshold to prevent noise triggering, the state machine sets to s13 and forces topswitch-hx to go through the entire auto- restart sequence before attempting to switch again. the ratio of ov and uv thresholds is preset at 4.5, as can be seen in figure 12. when the mosfet is off, the rectifed dc high voltage surge capability is increased to the voltage rating of the mosfet (700 v), due to the absence of the refected voltage and leakage spikes on the drain. the ov feature can be disabled independent of the uv feature. in order to reduce the no-load input power of topswitch-hx designs, the v-pin (or m-pin for p package) operates at very low currents. this requires careful layout considerations when designing the pcb to avoid noise coupling. traces and components connected to the v-pin should not be adjacent to any traces carrying switching currents. these include the drain, clamp network, bias winding return or power traces from other converters. if the line sensing features are used, then the sense resistors must be placed within 10 mm of the v-pin to minimize the v-pin node area. the dc bus should then be routed to the line sense resistors. note that external capacitance must not be connected to the v-pin as this may cause misoperation of the v pin related functions. hysteretic or latching output overvoltage protection (ovp) the detection of the hysteretic or latching output overvoltage protection (ovp) is through the trigger of the line overvoltage threshold. the v-pin or m-pin voltage will drop by 0.5 v, and the controller measures the external attached impedance immediately after this voltage drops. if i v or i m exceeds i ov(ls) (336 m a typical) longer than 100 m s, topswitch-hx will latch into a permanent off state for the latching ovp. it only can be reset if v v or v m goes below 1 v or v c goes below the power- up-reset threshold (v c(reset) ) and then back to normal. if i v or i m does not exceed i ov(ls) or exceeds no longer than 100 m s, topswitch-hx will initiate the line overvoltage and the hysteretic ovp. their behavior will be identical to the line overvoltage shutdown (ov) that has been described in detail in the previous section. voltage monitor and external current limit pin table* figure number 16 17 18 19 20 21 22 23 24 25 26 27 28 three terminal operation 3 line undervoltage 3 3 3 3 3 3 line overvoltage 3 3 3 3 3 3 line feed-forward (dc max ) 3 3 3 3 3 output overvoltage protection 3 3 overload power limiting 3 external current limit 3 3 3 3 3 remote on/off 3 3 3 device reset 3 * this table is only a partial list of many voltage monitor and external current limit pin confgurations that are possible. table 2. voltage monitor (v) pin and external current limit (x) pin confguration options. multi-function pin table* figure number 29 30 31 32 33 34 35 36 37 38 39 40 three terminal operation 3 line undervoltage 3 3 3 3 line overvoltage 3 3 3 3 line feed-forward (dc max ) 3 3 3 output overvoltage protection 3 3 overload power limiting 3 external current limit 3 3 3 3 remote on/off 3 3 3 device reset 3 * this table is only a partial list of many multi-functional pin confgurations that are possible. table 3. multi-function (m) pin confguration options.
rev. h 06/13 12 top252-262 www.powerint.com figure 12. multi-function (p and g package). voltage monitor and external current limit (y, e/l and m package) pin characteristics. -250 -200 -150 -100 -50 0 25 50 75 100 125 336 pi-4646-071708 output mosfet switching (enabled) (disabled) (non-latching) (latching) i limit (default) dc max (78%) current limit m pin v pin x pin maximum duty cycle v bg i i i i i uv i rem(n) i ov i ov(ls) pin voltage note: this figure provides idealized functional characteristics with typical performance values. please refer to the parametric table and typical performance characteristics sections of the data sheet for measured data. for a detailed description of each functional pin operation refer to the functional description section of the data sheet. x and v pins (y , e, l and m packages) and m pin (p and g packages) current (a) disabled when supply output goes out of regulation the circuit examples shown in figures 41, 42 and 43 show a simple method for implementing the primary sensed over- voltage protection. during a fault condition resulting from loss of feedback, output voltage will rapidly rise above the nominal voltage. the increase in output voltage will also result in an increase in the voltage at the output of the bias winding. a voltage at the output of the bias winding that exceeds of the sum of the voltage rating of the zener diode connected from the bias winding output to the v-pin (or m-pin) and v-pin (or m-pin) voltage, will cause a current in excess of i v or i m to be injected into the v-pin (or m-pin), which will trigger the ovp feature. the primary sensed ovp protection circuit shown in figures 41, 42 and 43 is triggered by a signifcant rise in output voltage (and therefore bias winding voltage). if the power supply is operating under heavy load or low input line conditions when an open loop occurs, the output voltage may not rise signifcantly. under these conditions, a latching shutdown will not occur until load or line conditions change. nevertheless, the operation provides the desired protection by preventing signifcant rise in the output voltage when the line or load conditions do change. primary side ovp protection with the topswitch-hx in a typical application will prevent a nominal 12 v output from rising above approximately 20 v under open loop conditions. if greater accuracy is required, a secondary sensed ovp circuit is recommended.
rev. h 06/13 13 top252-262 www.powerint.com line feed-forward with dc max reduction the same resistor used for uv and ov also implements line voltage feed-forward, which minimizes output line ripple and reduces power supply output sensitivity to line transients. note that for the same control pin current, higher line voltage results in smaller operating duty cycle. as an added feature, the maximum duty cycle dc max is also reduced from 78% (typical) at a voltage slightly lower than the uv threshold to 36% (typical) at the ov threshold. dc max of 36% at high line was chosen to ensure that the power capability of the topswitch-hx is not restricted by this feature under normal operation. topswitch-hx provides a better ft to the ideal feed-forward by using two reduction slopes: -1% per m a for all bus voltage less than 195 v (typical for 4 m w line impedance) and -0.25% per m a for all bus voltage more than 195 v. this dual slope line feed-forward improves the line ripple rejection signifcantly compared with the topswitch-gx. remote on/off t opswitch-hx can be turned on or off by controlling the current into the voltage-monitor pin or out from the external current limit pin (y, e/l and m packages) and into or out from the multi-function pin (p and g package, see figure 12). in addition, the voltage-monitor pin has a 1 v threshold comparator connected at its input. this voltage threshold can also be used to perform remote on/off control. when a signal is received at the voltage-monitor pin or the external current limit pin (y, e/l and m packages) or the multi-function pin (p and g package) to disable the output through any of the pin functions such as ov, uv and remote on/off, topswitch-hx always completes its current switching cycle before the output is forced off. as seen above, the remote on/off feature can also be used as a standby or power switch to turn off the topswitch-hx and keep it in a very low power consumption state for indefnitely long periods. if the topswitch-hx is held in remote off state for long enough time to allow the control pin to discharge to the internal supply undervoltage threshold of 4.8 v (approximately 32 ms for a 47 m f control pin capacitance), the control pin goes into the hysteretic mode of regulation. in this mode, the control pin goes through alternate charge and discharge cycles between 4.8 v and 5.8 v (see control pin operation section above) and runs entirely off the high voltage dc input, but with very low power consumption (160 mw typical at 230 vac with m or x pins open). when the topswitch-hx is remotely turned on after entering this mode, it will initiate a normal start-up sequence with soft-start the next time the control pin reaches 5.8 v. in the worst case, the delay from remote on to start-up can be equal to the full discharge/charge cycle time of the control pin, which is approximately 125 ms for a 47 m f control pin capacitor. this reduced consumption remote off mode can eliminate expensive and unreliable in-line mechanical switches. it also allows for microprocessor controlled turn-on and turn-off sequences that may be required in certain applications such as inkjet and laser printers. soft-start the 17 ms soft-start sweeps the peak drain current and switching frequency linearly from minimum to maximum value by operating through the low frequency pwm mode and the variable frequency mode before entering the full frequency mode. in addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after being in hysteretic regulation of control pin voltage (v c ), due to remote off or thermal shutdown conditions. this effectively minimizes current and voltage stresses on the output mosfet, the clamp circuit and the output rectifer during start-up. this feature also helps minimize output overshoot and prevents saturation of the transformer during start-up. shutdown/auto-restart to minimize topswitch-hx power dissipation under fault conditions, the shutdown/auto-restart circuit turns the power supply on and off at an auto-restart duty cycle of typically 2% if an out of regulation condition persists. loss of regulation interrupts the external current into the control pin. v c regulation changes from shunt mode to the hysteretic auto- restart mode as described in control pin operation section. when the fault condition is removed, the power supply output becomes regulated, v c regulation returns to shunt mode, and normal operation of the power supply resumes. hysteretic over-temperature protection temperature protection is provided by a precision analog circuit that turns the output mosfet off when the junction temperature exceeds the thermal shutdown temperature (142 c typical). when the junction temperature cools to below the lower hysteretic temperature point, normal operation resumes, thus providing automatic recovery. a large hysteresis of 75 c (typical) is provided to prevent overheating of the pc board due to a continuous fault condition. v c is regulated in hysteretic mode, and a 4.8 v to 5.8 v (typical) triangular waveform is present on the control pin while in thermal shutdown. bandgap reference a ll critical topswitch-hx internal voltages are derived from a temperature-compensated bandgap reference. this voltage reference is used to generate all other internal current references, which are trimmed to accurately set the switching frequency, mosfet gate drive current, current limit, and the line ov/uv/ovp thresholds. topswitch-hx has improved circuitry to maintain all of the above critical parameters within very tight absolute and temperature tolerances. high-voltage bias current source this high-voltage current source biases topswitch-hx from the drain pin and charges the control pin external capacitance during start-up or hysteretic operation. hysteretic operation occurs during auto-restart, remote off and over-temperature shutdown. in this mode of operation, the current source is switched on and off, with an effective duty cycle of approxi- mately 35%. this duty cycle is determined by the ratio of control pin charge (i c ) and discharge currents (i cd1 and i cd2 ). this current source is turned off during normal operation when the output mosfet is switching. the effect of the current source switching will be seen on the drain voltage waveform as small disturbances and is normal.
rev. h 06/13 14 top252-262 www.powerint.com v bg + v t 1 v v ref 200 a 400 a control (c) (voltage sense) (positive current sense - undervoltage, overvoltage, on/off, maximum duty cycle reduction, output over- voltage protection) (negative current sense - on/off, current limit adjustment) pi-4714-071408 topswitch-hx voltage monitor (v) external current limit (x) y, e/l and m package v bg + v t v ref 200 a 400 a control (c) multi-function (m) (positive current sense - undervoltage, overvoltage, maximum duty cycle reduction, output overvoltage protection) (negative current sense - on/off, current limit adjustment) pi-4715-071408 topswitch-hx p and g package figure 13a. voltage monitor (v) and external current limit (x) pin input simplifed schematic. figure 13b. multi-function (m) pin input simplifed schematic.
rev. h 06/13 15 top252-262 www.powerint.com typical uses of frequency (f) pin pi-2654-071700 dc input voltage + - d s c control f pi-2655-071700 dc input voltage + - d s c control f figure 14. full frequency operation (132 khz). figure 15. half frequency operation (66 khz).
rev. h 06/13 16 top252-262 www.powerint.com typical uses of voltage monitor (v) and external current limit (x) pins x f pi-4716-020508 dc input voltage + - d c s d s c control v v x c s f d d s c d c x v s s s s s top254-258y top252-258m pi-4717-120307 dc input voltage + - d s c control v 4 m? r ls v uv = i uv r ls + v v (i v = i uv ) v ov = i ov r ls + v v (i v = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @100 vdc = 76% dc max @375 vdc = 41% pi-4756-121007 dc input voltage sense output voltage + - d v s c v uv = i uv r ls + v v (i v = i uv ) v ov = i ov r ls + v v (i v = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @ 100 vdc = 76% dc max @ 375 vdc = 41% control r ls 4 m? 10 k? reset q r pi-4719-120307 dc input voltage sense output voltage + - d v s c v uv = i uv r ls + v v (i v = i uv ) v ov = i ov r ls + v v (i v = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @ 100 vdc = 76% dc max @ 375 vdc = 41% control r ls 4 m? r ovp >3k? vr ovp r ovp figure 16a. three terminal operation (voltage monitor and external current limit features disabled. frequency pin tied to source or control pin) for top254-258 y packages. figure 17. line-sensing for undervoltage, overvoltage and line feed-forward. figure 18. line-sensing for undervoltage, overvoltage, line feed-forward and latched output overvoltage protection. figure 19. line-sensing for undervoltage, overvoltage, line feed-forward and hysteretic output overvoltage protection. figure 16c. three terminal operation (voltage monitor and external current limit features disabled. frequency pin tied to source or control pin) for top252-262 l and e packages. x g pi-4984-020708 dc input voltage + - d c s d s c control v top259-261y v x c s g d figure 16b. three terminal operation (voltage monitor and external current limit features disabled for top259-261 y packages. x f dc input voltage + - d c s d s c control v v x c s f d c s d pi-4956-071708 esip e package v x c s f d esip l package
rev. h 06/13 17 top252-262 www.powerint.com pi-4720-120307 dc input voltage + - d v s c v uv = r ls i uv + v v (i v = i uv ) for values shown v uv = 103.8 vdc r ls 6.2 v 4 m? 40 k? control pi-4721-120307 dc input voltage + - d s c control v 4 m? 55 k? r ls 1n4148 v ov = i ov r ls + v v (i v = i ov ) for values shown v ov = 457.2 vdc figure 20. line sensing for undervoltage only (overvoltage disabled). figure 21. line-sensing for overvoltage only (undervoltage disabled). maximum duty cycle reduced at low line and further reduction with increasing line voltage. typical uses of voltage monitor (v) and external current limit (x) pins (cont.) figure 22. external set current limit. x pi-4722-021308 dc input voltage + - d s c r il for r il = 12 k? i limit = 61% see figure 55b for other resistor values (r il ). top259-261yn would use the g pin as the return for r il . for r il = 19 k? i limit = 37% control x pi-4723-011008 dc input voltage + - d s c 2.5 m? r ls 6 k? r il 100% @ 100 vdc 53% @ 300 vdc i limit = i limit = top259-261yn would use the g pin as the return for r il . control x pi-2625-011008 dc input voltage + - d s c on/off 47 k? q r can be an optocoupler output or can be replaced by a manual switch. top259-261yn would use the g pin as the return for q r . q r control x on/off 16 k? pi-4724-011008 dc input voltage + - d s c r il q r 12 k? for r il = i limit = 61% 19 k? for r il = i limit = 37% q r can be an optocoupler output or can be replaced by a manual switch. control top259-261yn would use the g pin as the return for q r . figure 23. current limit reduction with line voltage. figure 24. active-on (fail safe) remote on/off. figure 25. active-on remote on/off with externally set current limit.
rev. h 06/13 18 top252-262 www.powerint.com typical uses of voltage monitor (v) and external current limit (x) pins (cont.) pi-4727-061207 dc input voltage + - d s c control m d s s s d s c s c m pi-4728-120307 dc input voltage + - d m s c v uv = i uv r ls + v m (i m = i uv ) v ov = i ov r ls + v m (i m = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @ 100 vdc = 76% dc max @ 375 vdc = 41% control r ls 4 m? figure 29. three terminal operation (multi-function features disabled). figure 30. line sensing for undervoltage, overvoltage and line feed-forward. figure 28. line-sensing for undervoltage, overvoltage, line feed-forward and latched output overvoltage protection with device reset. pi-4756-121007 dc input voltage sense output voltage + - d v s c v uv = i uv r ls + v v (i v = i uv ) v ov = i ov r ls + v v (i v = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @ 100 vdc = 76% dc max @ 375 vdc = 41% control r ls 4 m? 10 k? reset q r typical uses of multi-function (m) pin x on/off 16 k? pi-4725-011008 dc input voltage + - d s c control v r il r ls q r 4 m? v uv = i uv r ls + v v (i v = i uv ) v ov = i ov r ls + v v (i v = i ov ) dc max @100 vdc = 76% dc max @375 vdc = 41% 12 k? for r il = i limit = 61% q r can be an optocoupler output or can be replaced by a manual switch. top259-261yn would use the g pin as the return for q r . x pi-4726-021308 dc input voltage + - d s c control v r il r ls 12 k? 4 m? v uv = i uv x r ls + v v (i v = i uv ) v ov = i ov x r ls + v v (i v = i ov ) for r ls = 4 m? dc max @ 100 vdc = 76% dc max @ 375 vdc = 41% for r il = 12 k? i limit = 61% see figure 55b for other resistor values (r il ) to select different i limit values. v uv = 102.8 vdc v ov = 451 vdc top259-261yn would use the g pin as the return for r il . figure 26. active-on remote on/off with line-sense and external current limit. figure 27. line sensing and externally set current limit.
rev. h 06/13 19 top252-262 www.powerint.com pi-4729-120307 dc input voltage sense output voltage + - d m s c v uv = i uv r ls + v m (i m = i uv ) v ov = i ov r ls + v m (i m = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @ 100 vdc = 76% dc max @ 375 vdc = 41% control r ls 4 m? figure 31. line sensing for undervoltage, overvoltage, line feed-forward and latched output overvoltage protection. pi-4730-120307 dc input voltage sense output voltage + - d m s c v uv = i uv r ls + v m (i m = i uv ) v ov = i ov r ls + v m (i m = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @ 100 vdc = 76% dc max @ 375 vdc = 41% control r ls 4 m? vr ovp r ovp r ovp >3k? figure 32. line sensing for undervoltage, overvoltage, line feed-forward and hysteretic output overvoltage protection. pi-4731-120307 dc input voltage + - d m s c v uv = r ls i uv + v m (i m = i uv ) for values shown v uv = 103.8 vdc r ls 6.2 v 4 m? 40 k? control pi-4732-120307 dc input voltage + - d m s c v ov = i ov r ls + v m (i m = i ov ) for values shown v ov = 457.2 vdc control r ls 1n4148 4 m? 55 k? figure 33. line sensing for undervoltage only (overvoltage disabled). figure 34. line sensing for overvoltage only (undervoltage disabled). maximum duty cycle reduced at low line and further reduction with increasing line voltage. typical uses of multi-function (m) pin (cont.) figure 35. externally set current limit (not normally required C see m pin operation description). pi-4733-021308 dc input voltage + - d m s c for r il = 12 k? i limit = 61% control r il see figures 55b for other resistor values (r il ) to select different i limit values. for r il = 19 k? i limit = 37% pi-4734-092107 dc input voltage + - d m s c control r il r ls 2.5 m? 6 k? 100% @ 100 vdc 53% @ 300 vdc i limit = i limit = figure 36. current limit reduction with line voltage (not normally required C see m pin operation description).
rev. h 06/13 20 top252-262 www.powerint.com typical uses of multi-function (m) pin (cont.) pi-4757-120307 dc input voltage sense output voltage + - d m s c v uv = i uv r ls + v m (i m = i uv ) v ov = i ov r ls + v m (i m = i ov ) for r ls = 4 m? v uv = 102.8 vdc v ov = 451 vdc dc max @ 100 vdc = 76% dc max @ 375 vdc = 41% control r ls 4 m? 10 k? q r reset figure 40. line-sensing for undervoltage, overvoltage, line feed-forward and latched output overvoltage protection with device reset. pi-4736-060607 dc input voltage + - d s c r il r mc 24 k? 12 k? m control q r 2r il r mc = q r can be an optocoupler output or can be replaced by a manual switch. on/off 7 k? figure 39. active-off remote on/off with externally set current limit (see m pin operation description). pi-4735-092107 dc input voltage + - d s c q r r il m control 12 k? for r il = i limit = 61% q r can be an optocoupler output or can be replaced by a manual switch. on/off 16 k? 19 k? for r il = i limit = 37% figure 38. active-on remote on/off with externally set current limit (see m pin operation description). pi-2519-040501 dc input voltage + - d s c q r on/off m control q r can be an optocoupler output or can be replaced by a manual switch. 47 k? figure 37. active-on (fail safe) remote on/off.
rev. h 06/13 21 top252-262 www.powerint.com application examples a high effciency, 35 w, dual output - universal input power supply the circuit in figure 41 takes advantage of several of the topswitch-hx features to reduce system cost and power supply size and to improve effciency. this design delivers 35 w total continuous output power from a 90 vac to 265 vac input at an ambient of 50 oc in an open frame confguration. a nominal effciency of 84% at full load is achieved using top258p. with a dip-8 package, this design provides 35 w continuous output power using only the copper area on the circuit board underneath the part as a heat sink. the different operating modes of the topswitch-hx provide signifcant improvement in the no-load, standby, and light load performance of the power supply as compared to the previous generations of the topswitch. resistors r3 and r4 provide line sensing, setting line uv at 100 vdc and line ov at 450 vdc. diode d5, together with resistors r6, r7, capacitor c6 and tvs vr1, forms a clamp network that limits the drain voltage of the topswitch after the integrated mosfet turns off. tvs vr1 provides a defned maximum clamp voltage and typically only conducts during fault conditions such as overload. this allows the rcd clamp (r6, r7, c6 and d5) to be sized for normal operation, thereby maximizing effciency at light load. should the feedback circuit fail, the output of the power supply may exceed regulation limits. this increased voltage at output will also result in an increased voltage at the output of the bias winding. zener vr2 will break down and current will fow into the m pin of the topswitch initiating a hysteretic overvoltage protection with automatic restart attempts. resistor r5 will limit the current into the m pin to < 336 m a, thus setting hysteretic ovp. if latching ovp is desired, the value of r5 can be reduced to 20 w . the output voltage is controlled using the amplifer tl431. diode d9, capacitor c20 and resistor r16 form the soft fnish circuit. at startup, capacitor c20 is discharged. as the output voltage starts rising, current fows through the optocoupler diode inside u2a, resistor r13 and diode d9 to charge capacitor c20. this provides feedback to the circuit on the primary side. the current in the optocoupler diode u2a gradually decreases as the capacitor c20 becomes charged and the control amplifer ic u3 becomes operational. this ensures that the output voltage increases gradually and settles to the fnal value without any overshoot. resistor r16 ensures that the capacitor c20 is maintained charged at all times after startup, which effectively isolates c20 from the feedback circuit after startup. capacitor c20 discharges through r16 when the supply shuts down. resistors r20, r21 and r18 form a voltage divider network. the output of this divider network is primarily dependent on the divider circuit formed using r20 and r21 and will vary to some extent for changes in voltage at the 15 v output due to the connection of resistor r18 to the output of the divider network. resistor r19 and zener vr3 improve cross regulation in case only the 5 v output is loaded, which results in the 12 v output operating at the higher end of the specifcation. figure 41. 35 w dual output power supply using top258pn. d s c m control pi-4747-020508 r11 33 ? r12 33 ? r3 2.0 m? r16 10 k? r17 10 k? r21 10 k? 1% r18 196 k? 1% r19 10 ? r14 22 ? r13 330 ? r15 1 k? r20 12.4 k? 1% d9 1n4148 u3 tl431 2% vr3 bzx55b8v2 8.2 v 2% r7 20 ? 1/2 w vr2 1n5250b 20 v vr1 p6ke200a d5 fr106 r4 2.0 m? r5 5.1 k? r1 1 m? r2 1 m? r8 6.8 ? r10 4.7 ? r6 22 k? 2 w u2b ps2501- 1-h-a u2a ps2501- 1-h-a l2 3.3 h l1 6.8 mh l3 3.3 h u1 top258pn c9 47 f 16 v c20 10 f 50 v c21 220 nf 50 v c19 1.0 f 50 v c10 10 f 50 v c11 2.2 nf 250 vac d6 fr106 d8 sb530 d7 sb560 c8 100 nf 50 v d1 1n4937 d2 1n4007 d3 1n4937 d4 1n4007 c13 680 f 25 v c14 680 f 25 v c15 220 f 25 v c18 220 f 10 v c17 2200 f 10 v c12 470 pf 100 v c16 470 pf 100 v 2 t1 eer28 7 11 9 3 6 5 4 c4 100 f 400 v c6 3.9 nf 1 kv c7 2.2 nf 250 vac c3 220 nf 275 vac rt1 10 ? f1 3.15 a topswitch-hx l e n +12 v, 2 a rtn +5 v, 2.2 a rtn t o 90 - 265 vac
rev. h 06/13 22 top252-262 www.powerint.com a high effciency, 150 w, 250 C 380 vdc input power supply the circuit shown in figure 42 delivers 150 w (19 v @ 7.7 a) at 84% effciency using a top258y from a 250 vdc to 380 vdc input. a dc input is shown, as typically at this power level a power factor correction stage would precede this supply, providing the dc input. capacitor c1 provides local decoupling, necessary when the supply is remote from the main pfc output capacitor. the fyback topology is still usable at this power level due to the high output voltage, keeping the secondary peak currents low enough so that the output diode and capacitors are reasonably sized. in this example, the top258yn is at the upper limit of its power capability. resistors r3, r6 and r7 provide output power limiting, maintaining relatively constant overload power with input voltage. line sensing is implemented by connecting a 4 m w resistor from the v pin to the dc rail. resistors r4 and r5 together form the 4 m w line sense resistor. if the dc input rail rises above 450 vdc, then topswitch-hx will stop switching until the voltage returns to normal, preventing device damage. due to the high primary current, a low leakage inductance transformer is essential. therefore, a sandwich winding with a copper foil secondary was used. even with this technique, the leakage inductance energy is beyond the power capability of a simple zener clamp. therefore, r1, r2 and c3 are added in parallel to vr1 and vr3, two series tvs diodes being used to reduce dissipation. during normal operation, very little power is dissipated by vr1 and vr3, the leakage energy instead being dissipated by r1 and r2. however, vr1 and vr3 are essential to limit the peak drain voltage during start-up and/or overload conditions to below the 700 v rating of the topswitch-hx mosfet. the schematic shows an additional turn-off snubber circuit consisting of r20, r21, r22, d5 and c18. this reduces turn-off losses in the topswitch-hx. the secondary is rectifed and smoothed by d2, d3 and c5, c6, c7 and c8. two windings are used and rectifed with separate diodes d2 and d3 to limit diode dissipation. four capacitors are used to ensure their maximum ripple current specifcation is not exceeded. inductor l1 and capacitors c15 and c16 provide switching noise fltering. output voltage is controlled using a tl431 reference ic and r15, r16 and r17 to form a potential divider to sense the output voltage. resistor r12 and r24 together limit the optocoupler led current and set overall control loop dc gain. control loop compensation is achieved using components c12, c13, c20 and r13. diode d6, resistor r23 and capacitor c19 form a soft fnish network. this feeds current into the control pin prior to output regulation, preventing output voltage overshoot and ensuring startup under low line, full load conditions. suffcient heat sinking is required to keep the topswitch-hx device below 110 c when operating under full load, low line and maximum ambient temperature. airfow may also be required if a large heat sink area is not acceptable. l1 d4 1n4148 c11 100 nf 50 v +19 v, 7.7 a rtn rt1 5 ? r19 4.7 ? d3 mbr20100ct r7 4.7 m ? d2 mbr20100ct c15-c16 820 f 25 v c14 47 pf 1 kv r20 1.5 k? 2 w c10 47 f 10 v d1 byv26c t1 ei35 11 4 13,14 5 12 1 9,10 7 r15 4.75 k? 1% c20 1.0 f 50 v c17 47 pf 1 kv c9 10 f 50 v r23 15 k? 0.125 w r14 22 ? 0.5 w r3 8.06 k? 1% c4 2.2 nf 250 vac r10 6.8 ? c3 4.7 nf 1 kv c1 22 f 400 v r22 1.5 k? 2 w d6 1n4148 r8 4.7 r1 68 k? 2 w f1 4 a c18 120 pf 1 kv r16 31.6 k? 1% r2 68 k? 2 w vr2 1n5258b 36 v r11 1 k? 0.125 w c19 10 f 50 v r12 240 ? 0.125 w u1 top258yn r24 30 ? 0.125 w c5-c8 25 v vr1, vr3 p6ke100a r18 22 ? 0.5 w r21 2 w d5 1n4937 u2 pc817a u3 tl431 2% c12 4.7 nf 50 v r17 562 ? 1% r13 56 k? 0.125 w c13 100 nf 50 v ? u2 pc817b 3.3 h r4 2.0 m? r5 2.0 ? 1.5 k? t o topswitch-hx r6 4.7 m ? 820 f 250 - 380 vdc pi-4795-092007 d s c v f x control figure 42. 150 w, 19 v power supply using top258yn.
rev. h 06/13 23 top252-262 www.powerint.com a high effciency, 20 w continuous C 80 w peak, universal input power supply the circuit shown in figure 43 takes advantage of several of topswitch-hx features to reduce system cost and power supply size and to improve power supply effciency while delivering signifcant peak power for a short duration. this design delivers continuous 20 w and peak 80 w at 32 v from an 90 vac to 264 vac input. a nominal effciency of 82% at full load is achieved using top258mn. the m-package part has an optimized current limit to enable design of power supplies capable of delivering high power for a short duration. resistor r12 sets the current limit of the part. resistors r11 and r14 provide line feed forward information that reduces the current limit with increasing dc bus voltage, thereby maintaining a constant overload power level with increasing line voltage. resistors r1 and r2 implement the line undervoltage and overvoltage function and also provide feed forward compensation for reducing line frequency ripple at the output. the overvoltage feature inhibits topswitch-hx switching during a line surge extending the high voltage withstand to 700 v without device damage. the snubber circuit comprising of vr7, r17, r25, c5 and d2 limits the maximum drain voltage and dissipates energy stored in the leakage inductance of transformer t1. this clamp confguration maximizes energy effciency by preventing c5 from discharging below the value of vr7 during the lower frequency operating modes of topswitch-hx. resistor r25 damps high frequency ringing for reduced emi. a combined output overvoltage and over power protection circuit is provided via the latching shutdown feature of topswitch-hx and r20, c9, r22 and vr5. should the bias winding output voltage across c13 rise due to output overload or an open loop fault (opto coupler failure), then vr5 conducts triggering the latching shutdown. to prevent false triggering due to short duration overload, a delay is provided by r20, r22 and c9. to reset the supply following a latching shutdown, the v pin must fall below the reset threshold. to prevent the long reset delay associated with the input capacitor discharging, a fast ac reset circuit is used. the ac input is rectifed and fltered by d13 and c30. while the ac supply is present, q3 is on and q1 is off, allowing normal device operation. however when ac is removed, q1 pulls down the v pin and resets the latch. the supply will then return to normal operation when ac is again applied. transistor q2 provides an additional lower uv threshold to the level programmed via r1, r2 and the v pin. at low input ac voltage, q2 turns off, allowing the x pin to foat and thereby disabling switching. a simple feedback circuit automatically regulates the output voltage. zener vr3 sets the output voltage together with the voltage drop across series resistor r8, which sets the dc gain of the circuit. resistors r10 and c28 provide a phase boost to improve loop bandwidth. diodes d6 and d7 are low-loss schottky rectifers, and capacitor c20 is the output flter capacitor. inductor l3 is a common mode choke to limit radiated emi when long output cables are used and the output return is connected to safety earth ground. example applications where this occurs include pc peripherals, such as inkjet printers. c 8 1 nf 250 vac d 6-d7 c 9 1 f 100 v r17 1 k ? 0.5 w vr7 bzy97c150 150 v t 1 d 2 fr107 d13 1n4007 f 1 3 . 15 a c30 100 n f 400 v q 3 2n3904 r23 1 m ? c 1 220 n f 275 vac 90 - 264 vac r24 1 m ? l 1 5.3 mh 68 k ? d10 1n4007 c 3 120 f 400 v r11 3.6 m ? d 8 1n4007 rt1 10 ? r 1 2 m ? r14 3.6 m ? d 9 1n4007 q 2 2n3904 r18 39 k ? q 1 2n3904 r 2 2 m ? r 3 2 m ? r15 1 k ? r21 1 m ? 0.125 w r 4 2 m ? r26 c s d v x r22 2 m ? c 6 100 nf 50 v u 4 top258mn c 7 47 f 16 v vr5 1n5250b 20 v r25 c 5 10 n f 1 k v r 6 6.8 ? c10 1 n f 250 vac ef25 r20 130 k ? d 5 ll4148 c13 10 f 50 v u2a pc817d r 9 2 k ? r 8 1.5 k ? r10 5 6 ? vr3 1n5255b 28 v c28 330 n f 50 v r19 68 ? 0.5 w stps3150 c26 100 pf 1 kv l 3 47 h l 2 3 . 3 h c31 22 f 50 v c20 330 f 50 v r12 7.5 k ? 1 % d11 1n4007 100 ? control c29 220 nf 50 v t o 32 v 625 ma, 2.5 a pk rtn pi-4833-092007 1 9 10 5 2 3 4 nc topswitch-hx figure 43. 20 w continuous, 80 w peak, universal input power supply using top258mn.
rev. h 06/13 24 top252-262 www.powerint.com a high effciency, 65 w, universal input power supply the circuit shown in figure 44 delivers 65 w (19 v @ 3.42 a) at 88% effciency using a top260en operating over an input voltage range of 90 vac to 265 vac. capacitors c1 and c6 and inductors l1 and l2 provide common mode and differential mode emi fltering. capacitor c2 is the bulk flter capacitor that ensures low ripple dc input to the fyback converter stage. capacitor c4 provides decoupling for switching currents reducing differential mode emi. in this example, the top260en is used at reduced current limit to improve effciency. resistors r5, r6 and r7 provide power limiting, maintaining relatively constant overload power with input voltage. line sensing is implemented by connecting a 4 m w impedance from the v pin to the dc rail. resistors r3 and r4 together form the 4 m w line sense resistor. if the dc input rail rises above 450 vdc, then topswitch-hx will stop switching until the voltage returns to normal, preventing device damage. this circuit features a high effciency clamp network consisting of diode d1, zener vr1, capacitor c5 together with resistors r8 and r9. the snubber clamp is used to dissipate the energy of the leakage reactance of the transformer. at light load levels, very little power is dissipated by vr1 improving effciency as compared to a conventional rcd clamp network. the secondary output from the transformer is rectifed by diode d2 and fltered by capacitors c13 and c14. ferrite bead l3 and capacitors c15 form a second stage flter and effectively reduce the switching noise to the output. output voltage is controlled using a lm431 reference ic. resistor r19 and r20 form a potential divider to sense the output voltage. resistor r16 limits the optocoupler led current and sets the overall control loop dc gain. control loop compensation is achieved using c18 and r21. the components connected to the control pin on the primary side c8, c9 and r15 set the low frequency pole and zero to further shape the control loop response. capacitor c17 provides a soft fnish during startup. optocoupler u2 is used for isolation of the feedback signal. diode d4 and capacitor c10 form the bias winding rectifer and flter. should the feedback loop break due to a defective component, a rising bias winding voltage will cause the zener vr2 to break down and trigger the over voltage protection which will inhibit switching. an optional secondary side over voltage protection feature which offers higher precision (as compared to sensing via the bias winding) is implemented using vr3, r18 and u3. excess voltage at the output will cause current to fow through the optocoupler u3 led which in turn will inject current in the v-pin through resistor r13, thereby triggering the over voltage protection feature. figure 44. 65 w, 19 v power supply using top260en. pi-4998-021408 r16 33 ? r21 1 k? r20 10 k? r19 68.1 k? r18 47 ? r16 680 ? u4 lm431 2% vr3 bzx79-c22 22 v d1 dl4937 d6 1n4148 d3 bav19ws d5 bav19ws vr2 1n5248b 18 v vr1 bzy97c180 180 v r13 5.1 ? r14 100 ? r12 5.1 k? r11 2 m? r1 2.2 m? r2 2.2 m? r15 6.8 ? r10 73.2 k? r8 100 ? r9 1 k? u3b pc357a u3a pc357a u2b lty817c u2a lty817c l3 ferrite bead l1 12 mh l2 ferrite bead u1 top260en c9 47 f 16 v c16 1 f 50 v c17 33 f 35 v c18 100 nf c11 100 nf 50 v c10 22 f 50 v d4 bav19ws d2 mbr20100ct c8 100 nf 50 v c4 100 nf 400 v 3kbp08m br1 c13 470 f 25 v c14 470 f 25 v c15 47 f 25 v c12 1 nf 100 v 4 t1 rm10 fl1 fl2 5 3 2 6 c6 2.2 nf 250 vac c1 330 nf 275 vac f1 4 a topswitch-hx l e n 19 v, 3.42 a rtn c2 120 f 400 v c3 470 pf 250 vac c7 100 nf 25 v c5 2.2 nf 1 kv 90 - 265 vac d s c v f x control r3 2.0 m? r5 5.1 m? r4 2.0 m? r7 15 k? 1% r6 6.8 m?
rev. h 06/13 25 top252-262 www.powerint.com key application considerations topswitch-hx vs. topswitch-gx table 4 compares the features and performance differences between topswitch-hx and topswitch-gx. many of the new features eliminate the need for additional discrete components. other features increase the robustness of design, allowing cost savings in the transformer and other power components. topswitch-hx vs. topswitch-gx function topswitch-gx topswitch-hx topswitch-hx advantages ecosmart linear frequency reduction to 30 khz (@ 132 khz) for duty cycles < 10% multi-mode operation with linear frequency reduction to 30 khz (@ 132 khz) and multi-cycle modulation (virtually no audible noise) ? improved effciency over load (e.g. at 25% load point) ? improved standby effciency ? improved no-load consumption output overvoltage protection (ovp) not available user programmable primary or secondary hysteretic or latching ovp ? protects power supply output during open loop fault ? maximum design fexibility line feed-forward with duty cycle reduction linear reduction dual slope reduction with lower, more accurate onset point ? improved line ripple rejection ? smaller dc bus capacitor switching frequency dip-8 package 132 khz 66 khz ? increased output power for given mosfet size due to higher effciency lowest mosfet on resistance in dip-8 package 3.0 w (top246p) 1.8 w (top258p) ? increased output power in designs without external heat sink i 2 f trimming not available -10% / +20% ? increased output power for given core size ? reduced over-load power auto-restart duty cycle 5.6% 2% ? reduced delivered average output power during open loop faults frequency jitter 4 khz @ 132 khz 2 khz @ 66 khz 5 khz @ 132 khz 2.5 khz @ 66 khz ? reduced emi flter cost thermal shutdown 130 c to 150 c 135 c to 150 c ? increased design margin external current limit 30%-100% of i limit 30%-100% of i limit , additional trim at 0.7 i limit ? reduced tolerances when current limit is set externally line uv detection threshold 50 m a (2 m w sense impedance) 25 m a (4 m w sense impedance) ? reduced dissipation for lower no-load consumption soft-start 10 ms duty cycle and current limit ramp 17 ms sweep through multi-mode characteristic ? reduced peak current and voltage component stress at startup ? smooth output voltage rise table 4. comparison between topswitch-gx and topswitch-hx.
rev. h 06/13 26 top252-262 www.powerint.com topswitch-hx design considerations power table the data sheet power table (table 1) represents the maximum practical continuous output power based on the following conditions: 1. 12 v output. 2. schottky or high effciency output diode. 3. 135 v refected voltage (v or ) and effciency estimates. 4. a 100 vdc minimum for 85-265 vac and 250 vdc mini - mum for 230 vac. 5. suffcient heat sinking to keep device temperature 100 c. 6. power levels shown in the power table for the m/p package device assume 6.45 cm 2 of 610 g/m 2 copper heat sink area in an enclosed adapter, or 19.4 cm 2 in an open frame. the provided peak power depends on the current limit for the respective device. topswitch-hx selection selecting the optimum topswitch-hx depends upon required maximum output power, effciency, heat sinking constraints, system requirements and cost goals. with the option to externally reduce current limit, an y, e/l or m package topswitch-hx may be used for lower power applications where higher effciency is needed or minimal heat sinking is available. input capacitor the input capacitor must be chosen to provide the minimum dc voltage required for the topswitch-hx converter to maintain regulation at the lowest specifed input voltage and maximum output power. since topswitch-hx has a high dc max limit and an optimized dual slope line feed forward for ripple rejection, it is possible to use a smaller input capacitor. for topswitch-hx, a capacitance of 2 m f per watt is possible for universal input with an appropriately designed transformer. primary clamp and output refected voltage v or a primary clamp is necessary to limit the peak topswitch-hx drain to source voltage. a zener clamp requires few parts and takes up little board space. for good effciency, the clamp zener should be selected to be at least 1.5 times the output refected voltage v or , as this keeps the leakage spike conduction time short. when using a zener clamp in a universal input application, a v or of less than 135 v is recommended to allow for the absolute tolerances and temperature variations of the zener. this will ensure effcient operation of the clamp circuit and will also keep the maximum drain voltage below the rated breakdown voltage of the topswitch-hx mosfet. a high v or is required to take full advantage of the wider dc max of topswitch-hx. an rcd clamp provides tighter clamp voltage tolerance than a zener clamp and allows a vor as high as 150 v. rcd clamp dissipation can be minimized by reducing the external current limit as a function of input line voltage (see figures 23 and 36). the rcd clamp is more cost effective than the zener clamp but requires more careful design (see quick design checklist). output diode the output diode is selected for peak inverse voltage, output current, and thermal conditions in the application (including heat sinking, air circulation, etc.). the higher dc max of topswitch-hx, along with an appropriate transformer turns ratio, can allow the use of a 80 v schottky diode for higher effciency on output voltages as high as 15 v (see figure 41). bias winding capacitor due to the low frequency operation at no-load, a 10 m f bias winding capacitor is recommended. soft-start generally, a power supply experiences maximum stress at start-up before the feedback loop achieves regulation. for a period of 17 ms, the on-chip soft-start linearly increases the drain peak current and switching frequency from their low starting values to their respective maximum values. this causes the output voltage to rise in an orderly manner, allowing time for the feedback loop to take control of the duty cycle. this reduces the stress on the topswitch-hx mosfet, clamp circuit and output diode(s), and helps prevent transformer saturation during start-up. also, soft-start limits the amount of output voltage overshoot and, in many applications, eliminates the need for a soft-fnish capacitor. emi the frequency jitter feature modulates the switching frequency over a narrow band as a means to reduce conducted emi peaks associated with the harmonics of the fundamental switching frequency. this is particularly benefcial for average detection mode. as can be seen in figure 45, the benefts of jitter increase with the order of the switching harmonic due to an increase in frequency deviation. devices in the p, g or m package and top259-261yn operate at a nominal switching frequency of 66 khz. the frequency pin of devices in the top254-258 y and e packages offer a switching frequency option of 132 khz or 66 khz. in applications that require heavy snubber on the drain node for reducing high frequency radiated noise (for example, video noise sensitive applications such as vcrs, dvds, monitors, tvs, etc.), operating at 66 khz will reduce snubber loss, resulting in better effciency. also, in applications where transformer size is not a concern, use of the 66 khz option will provide lower emi and higher effciency. note that the second harmonic of 66 khz is still below 150 khz, above which the conducted emi specifcations get much tighter. for 10 w or below, it is possible to use a simple inductor in place of a more costly ac input common mode choke to meet worldwide conducted emi limits. transformer design it is recommended that the transformer be designed for maximum operating fux density of 3000 gauss and a peak fux density of 4200 gauss at maximum current limit. the turns ratio should be chosen for a refected voltage (v or ) no greater than 135 v when using a zener clamp or 150 v (max) when using an rcd clamp with current limit reduction with line voltage (overload protection). for designs where operating current is signifcantly lower than the default current limit, it is recommended to use an externally set current limit close to the operating peak current to reduce peak fux density and peak power (see figures 22 and 35). in most applications, the tighter current limit tolerance, higher switching frequency and soft-start features of topswitch-hx contribute to a smaller transformer when compared to topswitch-gx.
rev. h 06/13 27 top252-262 www.powerint.com figure 45b. topswitch-hx full range emi scan (132 khz with jitter) with identical circuitry and conditions. -20 -10 0 -10 20 30 40 50 60 70 80 0.15 1 10 30 frequency (mhz) amplitude (dbv) pi-2576-010600 en55022b (qp) en55022b (av) en55022b (qp) en55022b (av) -20 -10 0 -10 20 30 40 50 60 70 80 0.15 1 10 30 frequency (mhz) amplitude (dbv) pi-2577-010600 topswitch-hx (with jitter) figure 45a. fixed frequency operation without jitter. standby consumption frequency reduction can signifcantly reduce power loss at light or no load, especially when a zener clamp is used. for very low secondary power consumption, use a tl431 regulator for feedback control. a typical topswitch-hx circuit automatically enters mcm mode at no load and the low frequency mode at light load, which results in extremely low losses under no-load or standby conditions. high power designs the topswitch-hx family contains parts that can deliver up to 333 w. high power designs need special considerations. guidance for high power designs can be found in the design guide for topswitch-hx (an-43). topswitch-hx layout considerations the topswitch-hx has multiple pins and may operate at high power levels. the following guidelines should be carefully followed. primary side connections use a single point (kelvin) connection at the negative terminal of the input flter capacitor for the topswitch-hx source pin and bias winding return. this improves surge capabilities by returning surge currents from the bias winding directly to the input flter capacitor. the control pin bypass capacitor should be located as close as possible to the source and control pins, and its source connection trace should not be shared by the main mosfet switching currents. all source pin referenced components connected to the multi-function (m-pin), voltage monitor (v-pin) or external current limit (x-pin) pins should also be located closely between their respective pin and source. once again, the source connection trace of these components should not be shared by the main mosfet switching currents. it is very critical that source pin switching currents are returned to the input capacitor negative terminal through a separate trace that is not shared by the components connected to control, multi-function, voltage monitor or external current limit pins. this is because the source pin is also the controller ground reference pin. any traces to the m, v, x or c pins should be kept as short as possible and away from the drain trace to prevent noise coupling. voltage monitor resistors (r1 and r2 in figures 46, 47, 48, r3 and r4 in figure 49, and r14 in figure 50) should be located close to the m or v pin to minimize the trace length on the m or v pin side. resistors connected to the m, v or x pin should be connected as close to the bulk cap positive terminal as possible while routing these connections away from the power switching circuitry. in addition to the 47 f control pin capacitor, a high frequency bypass capacitor in parallel may be used for better noise immunity. the feedback optocoupler output should also be located close to the control and source pins of topswitch-hx and away from the drain and clamp component traces. y capacitor the y capacitor should be connected close to the secondary output return pin(s) and the positive primary dc input pin of the transformer. heat sinking the tab of the y package (to-220c) and e package (esip-7c) and l package (esip-7f) are internally electrically tied to the source pin. to avoid circulating currents, a heat sink attached to the tab should not be electrically tied to any primary ground/source nodes on the pc board. when using a p (dip-8), g (smd-8) or m (dip-10) package, a copper area underneath the package connected to the source pins will act as an effective heat sink. on double sided boards, topside and bottom side areas connected with vias can be used to increase the effective heat sinking area. in addition, suffcient copper area should be provided at the anode and cathode leads of the output diode(s) for heat sinking. in figures 46 to 50 a narrow trace is shown between the output rectifer and output flter capacitor. this trace acts as a thermal relief between the rectifer and flter capacitor to prevent excessive heating of the capacitor.
rev. h 06/13 28 top252-262 www.powerint.com figure 46. layout considerations for topswitch-hx using p package. figure 47. layout considerations for topswitch-hx using m package. + - dc out + - hv pi-4753-070307 y1- capacitor c6 isolation barrier output rectifier r1 r2 jp1 j1 c1 u1 r3 c2 r4 d1 vr1 c4 c3 r8 d2 vr2 c5 c9 d3 c7 l1 c8 j2 r8 r13 r14 r6 r7 jp2 r12 r11 r10 u3 r9 c10 t1 output filter capacitor input filter capacitor maximize hatched copper areas ( ) for optimum heat sinking u2 tr ansformer d s s s s c m optional pcb slot for external heatsink in contact with source pins + - dc out + - hv pi-4752-070307 isolation barrier output rectifier r1 jp1 j1 c1 u1 r5 c2 r6 d1 vr1 c4 r7 c3 r8 r9 d2 c5 d3 c7 l1 c8 j2 r11 r10 jp2 c9 r15 u3 r16 r17 r14 r12 t1 r13 vr2 r2 r3 r4 output filter capacitor input filter capacitor optional pcb slot for external heatsink in contact with source pins maximize hatched copper areas ( ) for optimum heat sinking s s d c x v s s s u2 y1- capacitor c6 tr ansformer
rev. h 06/13 29 top252-262 www.powerint.com figure 48. layout considerations for topswitch-hx using top254-258 y package. + - dc out + - hv pi-4751-070307 y1- capacitor c6 isolation barrier output rectifier r1 r2 r3 r4 jp1 j1 c1 u1 hs1 r3 c2 r4 d1 vr1 c4 r7 r10 r13 d2 vr2 c5 c9 d3 c7 l1 c8 j2 r9 r11 r16 r14 r8 jp2 r12 r17 r15 u3 r12 c10 t1 output filter capacitor input filter capacitor tr ansformer s f c x v d u2 figure 49. layout considerations for topswitch-hx using top259-261 y package. + - hv + - dc out pi-4977-021408 y1- capacitor c7 isolation barrier j1 j2 c4 hs1 r3 r22 r14 r8 c9 c8 u5 d5 r7 c6 r6 vr1 r9 r5 vr2 r10 d6 c10 jp2 r11 r4 l3 c17 d8 r12 c16 r15 u4 c21 r17 r13 r21 r20 c18 jp1 u2 t1 output filter capacitor input filter capacitor tr ansformer c g d v s x
rev. h 06/13 30 top252-262 www.powerint.com + - dc out + - hv pi-4975-022108 y1- capacitor c7 isolation barrier output rectifier r4 r3 r11 r5 u1 c9 r22 r8 r14 d6 c10 r10 jp2 u2 u4 hs1 r17 c21 r13 r15 r21 r9 vr2 r6 d5 r7 vr1 c6 c4 c8 h52 c17 c18 r20 l3 c19 d8 c16 r12 t1 output filter capacitor input filter capacitor tr ansformer j1 j2 x f d c s v figure 50a. layout considerations for topswitch-hx using e package and operating at 66 khz. + - hv + - dc out pi-4976-011410 y1- capacitor c7 isolation barrier t1 output rectifier r4 r3 r11 r5 j1 j2 u1 r6 d5 c6 r7 r8 c8 r22 d6 c10 r10 r9 vr2 c9 r14 vr1 hs1 c4 u2 r15 r13 r17 jp2 u4 c21 r21 r20 c19 l3 h52 d8 c16 r12 c18 c17 output filter capacitor input filter capacitor transformer x f d c s v figure 50b. layout considerations for topswitch-hx using e package and operating at 132 khz.
rev. h 06/13 31 top252-262 www.powerint.com quick design checklist in order to reduce the no-load input power of topswitch-hx designs, the v-pin (or m-pin for p package) operates at very low current. this requires careful layout considerations when designing the pcb to avoid noise coupling. traces and components connected to the v-pin should not be adjacent to any traces carrying switching currents. these include the drain, clamp network, bias winding return or power traces from other converters. if the line sensing features are used, then the sense resistors must be placed within 10 mm of the v-pin to minimize the v pin node area. the dc bus should then be routed to the line sense resistors. note that external capacitance must not be connected to the v-pin as this may cause misoperation of the v pin related functions. as with any power supply design, all topswitch-hx designs should be verifed on the bench to make sure that components specifcations are not exceeded under worst-case conditions. the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that peak v ds does not exceed 675 v at highest input voltage and maximum overload output power. maximum overload output power occurs when the output is overloaded to a level just before the power supply goes into auto-restart (loss of regulation). 2. maximum drain current C at maximum ambient temperature, maximum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of trans - former saturation and excessive leading edge current spikes. topswitch-hx has a leading edge blanking time of 220 ns to prevent premature termination of the on-cycle. verify that the leading edge current spike is below the allowed current limit envelope (see figure 53) for the drain current waveform at the end of the 220 ns blanking period. 3. thermal check C at maximum output power, both minimum and maximum voltage and ambient temperature; verify that temperature specifcations are not exceeded for topswitch-hx, transformer, output diodes and output capacitors. enough thermal margin should be allowed for the part-to-part variation of the r ds(on) of topswitch-hx, as specifed in the data sheet. the margin required can either be calculated from the values in the parameter table or it can be accounted for by connecting an external resistance in series with the drain pin and attached to the same heat sink, having a resistance value that is equal to the difference between the measured r ds(on) of the device under test and the worst case maximum specifcation. design tools up-to-date information on design tools can be found at the power integrations website: www.powerint.com figure 50c. layout considerations for topswitch-hx using l package and operating at 132 khz. + - dc out + - hv pi-5216-091508 y1- capacitor c7 isolation barrier output rectifier j1 r11 r3 r4 r5 r14 jp1 c4 r6 d5 c6 r7 vr1 r22 c8 r8 u1 c9 d6 c10 r10 vr2 r9 jp2 r15 r13 r17 u4 c21 r21 d8 c16 r12 hs2 hs1 c17 j2 r20 c19 l3 c18 t1 output filter capacitor input filter capacitor note: components u1, r8, c8, c9 and r22 are under heat sink hs1. transformer x f d y s c u2
rev. h 06/13 32 top252-262 www.powerint.com absolute maximum ratings (2) drain peak voltage ........................................... -0.3 v to 700 v drain peak current: top252 ......................................... 0.68 a drain peak current: top253 ......................................... 1.37 a drain peak current: top254 ......................................... 2.08 a drain peak current: top255 ......................................... 2.72 a drain peak current: top256 ......................................... 4.08 a drain peak current: top257 ......................................... 5.44 a drain peak current: top258 ......................................... 6.88 a drain peak current: top259 ......................................... 7.73 a drain peak current: top260 ......................................... 9.00 a drain peak current: top261 ....................................... 11.10 a drain peak current: top262 ....................................... 11.10 a control voltage ................................................. -0.3 v to 9 v control current ........................................................ 100 ma voltage monitor pin voltage ........................... -0.3 v to 9 v current limit pin voltage .............................. -0.3 v to 4.5 v multi-function pin voltage ............................... -0.3 v to 9 v frequency pin voltage ...................................... -0.3 v to 9 v storage temperature ...................................... -65 c to 150 c operating junction temperature ...................... -40 c to 150 c lead temperature (1) ........................................................ 260 c notes: 1. 1/16 in. from case for 5 seconds. 2. maximum ratings specifed may be applied one at a time without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. thermal impedance parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 54 (unless otherwise specifed) min typ max units control functions switching frequency in full frequency mode (average) f osc t j = 25 c frequency pin connected to source 119 132 145 khz top252-258y top255-262l top252-262e frequency pin connected to control 59.4 66 72.6 top252-258y top255-262l top252-262e top252-258p/g/m top259-261y 59.4 66 72.6 frequency jitter deviation d f 132 khz operation 5 khz 66 khz operation 2.5 frequency jitter modulation rate f m 250 hz maximum duty cycle dc max i c = i cd1 i v i v(dc) or i m i m(dc) or v v , v m = 0 v 75 78 83 % i v or i m = 95 m a 30 soft-start time t soft t j = 25 c 17 ms pwm gain dc reg t j = 25 c top252-255 -31 -25 -20 %/ma top256-258 -27 -22 -17 top259-262 -25 -20 -15 pwm gain temperature drift see note a -0.01 %/ma/c external bias current i b 66 khz operation top252-255 0.9 1.5 2.1 ma top256-258 1.0 1.6 2.2 top259-262 1.1 1.7 2.4 thermal impedance: y package: ( q ja ) ........................................... 80 c/w (1) ( q jc ) ............................................. 2 c/w (2) p, g and m packages: ( q ja ) ......................... . 70 c/w (3) ; 60 c/w (4) ( q jc ) .......................................... .11 c/w (5) e/l package: ( q ja ) ............................................105 c/w (1) ( q jc ) ............................................. 2 c/w (2) notes: 1. free standing with no heat sink. 2. measured at the back surface of tab. 3. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 4. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 5. measured on the source pin close to plastic interface.
rev. h 06/13 33 top252-262 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units control functions (cont.) external bias current i b 132 khz operation top252-255 1.0 1.6 2.2 ma top256-258 1.3 1.9 2.5 top259-262 1.6 2.2 2.9 control current at 0% duty cycle i c(off) 66 khz operation top252-255 4.4 5.8 ma top256-258 4.7 6.1 top259-262 5.1 6.5 132 khz operation top252-255 4.6 6.0 top256-258 5.1 6.5 top259-262 6.0 7.4 dynamic impedance z c i c = 4 ma; t j = 25 c, see figure 52 10 18 22 w dynamic impedance temperature drift 0.18 %/c control pin internal filter pole 7 khz upper peak current to set current limit ratio k ps(upper) t j = 25 c see note b 50 55 60 % lower peak current to set current limit ratio k ps(lower) t j = 25 c see note b 25 % multi-cycle- modulation switching frequency f mcm(min) t j = 25 c 30 khz minimum multi-cycle- modulation on period t mcm(min) t j = 25 c 135 m s shutdown/auto-restart control pin charging current i c(ch) t j = 25 c v c = 0 v -5.0 -3.5 -1.0 ma v c = 5 v -3.0 -1.8 -0.6 charging current temperature drift see note a 0.5 %/c auto-restart upper threshold voltage v c(ar)u 5.8 v auto-restart lower threshold voltage v c(ar)l 4.5 4.8 5.1 v multi-function (m), voltage monitor (v) and external current limit (x) inputs auto-restart hysteresis voltage v c(ar)hyst 0.8 1.0 v auto-restart duty cycle dc (ar) 2 4 % auto-restart frequency f (ar) 0.5 hz line undervoltage threshold current and hysteresis (m or v pin) i uv t j = 25 c threshold 22 25 27 m a hysteresis 14 m a line overvoltage threshold current and hysteresis (m or v pin) i ov t j = 25 c threshold 107 112 117 m a hysteresis 4 m a
rev. h 06/13 34 top252-262 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units multi-function (m), voltage monitor (v) and external current limit (x) inputs output overvoltage latching shutdown threshold current i ov(ls) t j = 25 c 269 336 403 m a v or m pin reset voltage v v(th) or v m(th) t j = 25 c 0.8 1.0 1.6 v remote on/off negative threshold current and hysteresis (m or x pin) i rem (n) t j = 25 c threshold -35 -27 -20 m a hysteresis 5 v or m pin short circuit current i v(sc) or i m(sc) t j = 25 c v v , v m = v c 300 400 500 m a x or m pin short circuit current i x(sc) or i m(sc) v x , v m = 0 v normal mode -260 -200 -140 m a auto-restart mode -95 -75 -55 v or m pin voltage (positive current) v v or v m i v or i m = i uv 2.10 2.8 3.20 v i v or i m = i ov top252-top257 2.79 3.0 3.21 top258-top262 2.83 3.0 3.25 v or m pin voltage hysteresis (positive current) v v(hyst) or v m(hyst) i v or i m = i ov 0.2 0.5 v x or m pin voltage (negative current) v x or v m i x or i m = -50 m a 1.23 1.30 1.37 v i x or i m = -150 m a 1.15 1.22 1.29 maximum duty cycle reduction onset threshold current i v(dc) or i m(dc) i c i b , t j = 25 c 18.9 22.0 24.2 m a maximum duty cycle reduction slope t j = 25 c i v(dc) < i v <48 m a or i m(dc) < i m <48 m a -1.0 %/ m a i v or i m 48 m a -0.25 remote off drain supply current i d(rmt) v drain = 150 v x, v or m pin floating 0.6 1.0 ma v or m pin shorted to control 1.0 1.6 remote on delay t r(on) from remote on to drain turn-on see note b 66 khz 3.0 m s 132 khz 1.5 remote off setup time t r(off) minimum time before drain turn-on to disable cycle see note b 66 khz 3.0 m s 132 khz 1.5 frequency input frequency pin threshold voltage v f see note b 2.9 v frequency pin input current i f t j = 25 c v f = v c 10 55 90 m a
rev. h 06/13 35 top252-262 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units circuit protection self protection current limit (see note c) i limit top252pn/gn/mn t j = 25 c di/dt = 45 ma/ m s 0.400 0.43 0.460 a top252en t j = 25 c di/dt = 90 ma/ m s 0.400 0.43 0.460 top253pn/gn t j = 25 c di/dt = 80 ma/ m s 0.697 0.75 0.803 top253mn t j = 25 c di/dt = 90 ma/ m s 0.790 0.85 0.910 top253en t j = 25 c di/dt = 180 ma/ m s 0.790 0.85 0.910 top254pn/gn t j = 25 c di/dt = 105 ma/ m s 0.93 1.00 1.07 top254mn t j = 25 c di/dt = 135 ma/ m s 1.209 1.30 1.391 top254yn/en t j = 25 c di/dt = 270 ma/ m s 1.209 1.30 1.391 top255pn/gn t j = 25 c di/dt = 120 ma/ m s 1.069 1.15 1.231 top255mn t j = 25 c di/dt = 175 ma/ m s 1.581 1.70 1.819 top255ln t j = 25 c di/dt = 350 ma/ m s 1.581 1.70 1.819 top255yn/en t j = 25 c di/dt = 350 ma/ m s 1.581 1.70 1.819 top256pn/gn t j = 25 c di/dt = 140 ma/ m s 1.255 1.35 1.445 top256mn t j = 25 c di/dt = 220 ma/ m s 1.953 2.10 2.247 top256ln t j = 25 c di/dt = 435 ma/ m s 1.953 2.10 2.247 top256yn/en t j = 25 c di/dt = 530 ma/ m s 2.371 2.55 2.729 top257pn/gn t j = 25 c di/dt = 155 ma/ m s 1.395 1.50 1.605 top257mn t j = 25 c di/dt = 265 ma/ m s 2.371 2.55 2.729 top257ln t j = 25 c di/dt = 530 ma/ m s 2.371 2.55 2.729 top257yn/en t j = 25 c di/dt = 705 ma/ m s 3.162 3.40 3.638 top258pn/gn t j = 25 c di/dt = 170 ma/ m s 1.534 1.65 1.766 top258mn t j = 25 c di/dt = 310 ma/ m s 2.790 3.00 3.210 top258ln t j = 25 c di/dt = 620 ma/ m s 2.790 3.00 3.210
rev. h 06/13 36 top252-262 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units circuit protection (cont.) self protection current limit (see note c) i limit top258yn/en t j = 25 c di/dt = 890 ma/ m s 3.999 4.30 4.601 a top259ln t j = 25 c di/dt = 720 ma/ m s 3.236 3.48 3.724 top259yn/en t j = 25 c di/dt = 1065 ma/ m s 4.790 5.15 5.511 top260ln t j = 25 c di/dt = 870 ma/ m s 3.906 4.20 4.494 top260yn/en t j = 25 c di/dt = 1240 ma/ m s 5.580 6.00 6.420 top261ln t j = 25 c di/dt = 1065 ma/ m s 4.808 5.17 5.532 top261yn/en t j = 25 c di/dt = 1530 ma/ m s 6.882 7.40 7.918 top262ln t j = 25 c di/dt = 1065 ma/ m s 4.808 5.17 5.532 top262en t j = 25 c di/dt = 1530 ma/ m s 6.882 7.40 7.918 initial current limit i init see note b 0.70 i limit(min) a power coeffcient p coeff t j = 25 c, see note d i x or i m - 165 m a 0.9 i 2 f i 2 f 1.2 i 2 f a 2 khz i x or i m - 117 m a 0.9 i 2 f i 2 f 1.2 i 2 f leading edge blanking time t leb t j = 25 c, see figure 53 220 ns current limit delay t il(d) 100 ns thermal shutdown temperature 135 142 150 c thermal shutdown hysteresis 75 c power-up reset threshold voltage v c(reset) figure 54 (s1 open condition) 1.75 3.0 4.25 v output on-state resistance r ds(on) top252 i d = 50 ma t j = 25 c 19.1 22.00 w t j = 100 c 28.8 33.40 top253 i d = 100 ma t j = 25 c 8.8 10.10 t j = 100 c 13.1 15.20 top254 i d = 150 ma t j = 25 c 5.4 6.25 t j = 100 c 8.35 9.70 top255 i d = 200 ma t j = 25 c 4.1 4.70 t j = 100 c 6.3 7.30 top256 i d = 300 ma t j = 25 c 2.8 3.20 t j = 100 c 4.1 4.75 top257 i d = 400 ma t j = 25 c 2.0 2.30 t j = 100 c 3.1 3.60 top258 i d = 500 ma t j = 25 c 1.7 1.95 t j = 100 c 2.5 2.90
rev. h 06/13 37 top252-262 www.powerint.com notes: a. for specifcations with negative values, a negative temperature coeffcient corresponds to an increase in magnitude with increas - ing temperature, and a positive temperature coeffcient corresponds to a decrease in magnitude with increasing temperature. b. guaranteed by characterization. not tested in production. c. for externally adjusted current limit values, please refer to figures 55a and 55b (current limit vs. external current limit resis - tance) in the typical performance characteristics section. the tolerance specifed is only valid at full current limit. d. i 2 f calculation is based on typical values of i limit and f osc, i.e. i limit(typ) 2 f osc , where f osc = 66 khz or 132 khz depending on package / f pin connection. see f osc specifcation for detail. e. the topswitch-hx will start up at 18 v dc drain voltage. the capacitance of electrolytic capacitors drops signifcantly at tempera - tures below 0 c. for reliable start up at 18 v in sub zero temperatures, designers must ensure that circuit capacitors meet recommended capacitance values. f. breakdown voltage may be checked against minimum bv dss specifcation by ramping the drain pin voltage up to but not exceeding minimum bv dss . parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units output (cont.) on-state resistance r ds(on) top259 i d = 600 ma t j = 25 c 1.45 1.70 w t j = 100 c 2.25 2.60 top260 i d = 700 ma t j = 25 c 1.20 1.40 t j = 100 c 1.80 2.10 top261 i d = 800 ma t j = 25 c 1.05 1.20 t j = 100 c 1.55 1.80 top262 i d = 900 ma t j = 25 c 0.90 1.05 t j = 100 c 1.35 1.55 drain supply voltage t j 85 c, see note e 18 v 36 off-state drain leakage current i dss v v , v m = floating, i c = 4 ma, v ds = 560 v, t j = 125 c 470 m a breakdown voltage bv dss v v , v m = floating, i c = 4 ma, t j = 25 c see note f 700 v rise time t r measured in a typical flyback converter application 100 ns fall time t f 50 ns supply voltage characteristics control supply/ discharge current i cd1 output mosfet enabled v x , v v , v m = 0 v 66 khz operation top252-255 0.6 1.2 2.0 ma top256-258 0.9 1.4 2.3 top259-262 1.1 1.6 2.5 132 khz operation top252-255 0.8 1.3 2.2 top256-258 1.1 1.6 2.5 top259-262 1.5 2.2 2.9 i cd2 output mosfet disabled v x , v v , v m = 0 v 0.3 0.6 1.3
rev. h 06/13 38 top252-262 www.powerint.com figure 51. duty cycle measurement. figure 52. control pin i-v characteristic. figure 53. drain current operating envelope. figure 54. topswitch-hx general test circuit. pi-2039-033001 drain voltage hv 0 v 90% 10% 90% t 2 t 1 d = t 1 t 2 120 100 80 40 20 60 0 5 6 7 8 9 control pin voltage (v) control pin current (ma) 1 slope dynamic impedance = pi-4737-061207 0.8 1.3 1.2 1.1 0.9 0.8 1.0 0 0 1 2 6 8 3 time ( s) drain current (normalized) pi-4758-061407 4 5 7 0.7 0.6 0.5 0.4 0.3 0.2 0.1 i init(min) t leb (blanking time) pi-4738-071408 5-50 v 5-50 v s4 40 v 0.1 f 47 f 470 5 w to p254-258 y, all e, l or m packages (x and v pins) p or g package (m pin) 470 0-300 k 0-60 k 0-60 k 0-300 k notes: 1. this test circuit is not applicable for current limit or output characteristic measurements. 2. for p, g and m packages, short all source pins together. d d s fx c v m c control to pswitch-hx s1 s5 s3 0-15 v s2 s gx c control to p259-261 y (x and v pins) 5-50 v 0-300 k
rev. h 06/13 39 top252-262 www.powerint.com figure 55a. normalized current limit vs. x or m pin current. figure 55b. normalized current limit vs. external current limit resistance. pi-4754-120307 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 -200 -150 -100 -50 0 i x or i m ( a ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 t ypical notes: 1. maximum and minimum levels are based on characterization. 2. t j = 0 o c to 125 o c. minimum maximum normalized current limit normalized di/d t pi-4755-120307 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 05 10 15 20 25 30 35 40 45 r il ( k ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 notes: 1. maximum and minimum levels are based on characterization. 2. t j = 0 o c to 125 o c. 3. includes the variation of x or m pin voltage ty pical maximum minimum normalized current limit normalized di/dt . typical performance characteristics
rev. h 06/13 40 top252-262 www.powerint.com typical performance characteristics (cont.) 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) breakdown voltage (normalized to 25 c) pi-176b-033001 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-4759-061407 output frequency (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-4760-061407 current limit (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 02 55 07 5 100 125 150 junction t emperature ( ? c) pi-4739-061507 current limit (normalized to 25 ? c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-4761-061407 overvoltage threshold (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-4762-061407 under-voltage threshold (normalized to 25 c) figure 56. breakdown voltage vs. temperature. figure 57. frequency vs. temperature. figure 58. internal current limit vs. temperature. figure 59. external current limit vs. temperature with r il = 10.5 k w . figure 60. overvoltage threshold vs. temperature. figure 61. undervoltage threshold vs. temperature.
rev. h 06/13 41 top252-262 www.powerint.com typical performance characteristics (cont.) 6 4.5 5.5 5 2 0 100 200 500 400 300 voltage-monitor pin current ( a) voltage monitor pin voltage (v) pi-4740-060607 3 2.5 3.5 4 1.6 1.0 1.4 1.2 0 -200 -150 -50 -100 0 external current limit pin current ( a) external current limit pin voltage (v) pi-4741-110907 0.4 0.2 0.6 0.8 v x = 1.354 - 1147.5 ?i x ? + 1.759 10 6 (i x ) 2 with -180 a < i x < -25 a 6 5 4 3 2 1 0 -200 -100 0 100 200 300 400 500 pi-4742-021308 multi-function pin voltage (v) multi-function pin current ( a) see expanded version (figure 63b) 1.2 1.4 1.6 0.4 0.6 0.2 0.8 1.0 0 -200 -150 -50 -100 0 multi-function pin voltage (v) pi-4743-061407 multi-function pin current ( a) v m = 1.354 - 1147.5 ?i m ? + 1.759 10 6 (i m ) 2 with -180 a < i m < -25 a 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-4763-072208 control current (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-4764-061407 onset threshold current (normalized to 25 c) figure 62b. external current limit pin voltage vs. current. figure 63a. multi-function pin voltage vs. current. figure 63b. multi-function pin voltage vs. current (expanded). figure 64. control current out at 0% duty cycle vs. temperature. figure 65. maximum duty cycle reduction onset threshold current vs. temperature. figure 62a. voltage-monitor pin vs. current.
rev. h 06/13 42 top252-262 www.powerint.com typical performance characteristics (cont.) 1 -0.5 0 0.5 -2.5 0 20 40 60 80 100 drain pin voltage (v) control pin current (ma) pi-4744-072208 -1.5 -2 -1 v c = 5 v figure 66. output characteristics. figure 67. i c vs. drain voltage. figure 68. c oss vs. drain voltage. figure 69. drain capacitance power. figure 70. remote off drain supply current vs. temperature. 5 0 0 2 4 6 8 10 12 14 16 18 20 drain voltage (v) drain current (a) pi-4748-071708 2 1 t case = 25 c t case = 100 c 4 3 top262 1.82 top261 1.62 top260 1.42 top259 1,17 top258 1.00 top257 0.85 top256 0.61 top255 0.42 top254 0.32 top253 0.20 top252 0.10 scaling factors: 0 100 200 300 400 500 600 10 100 1000 10000 pi-4749-071708 drain pin voltage (v) drain capacitance (pf) top262 1.82 top261 1.62 top260 1.42 top259 1.17 top258 1.00 top257 0.85 top256 0.61 top255 0.42 top254 0.32 top253 0.20 top252 0.10 scaling factors: 500 400 200 100 300 0 0 200 100 400 500 600 300 700 drain pin voltage (v) power (mw) pi-4750-071708 132 khz 66 khz top262 1.82 top261 1.62 top260 1.42 top259 1.17 top258 1.00 top257 0.85 top256 0.61 top255 0.42 top254 0.32 top253 0.20 top252 0.10 scaling factors: 1.2 0.8 1.0 0 -50 0 -25 50 25 100 75 125 150 junction temperature ( c) remote off drain supply current (normalized to 25 c) pi-4745-061407 0.2 0.4 0.6
rev. h 06/13 43 top252-262 www.powerint.com pi-2644-040110 notes: 1. contr olling dimensions ar e inches. millimeter dimensions ar e shown in par entheses. 2. pin numbers start with pin 1, and continue fr om left to right when viewed fr om the fr ont. 3. dimensions do not include mold ?ash or other pr otrusions. mold ?ash or pr otrusions shall not exceed .006 (.15 mm) on any side. 4. minimum metal to metal spacing at the package body for omitted pin locations is .068 in. (1.73 mm). 5. position of terminals to be measur ed at a location .25 (6.35) below the package body . 6. all terminals ar e solder plated. y07c pin 1 pin 7 mounting hole pattern .050 (1.27) .150 (3.81) .050 (1.27) .150 (3.81) .050 (1.27) .050 (1.27) .100 (2.54) .180 (4.58) .200 (5.08) pin 1 + .010 (.25) m .461 (11.71) .495 (12.57) .390 (9.91) .420 (10.67) .146 (3.71) .156 (3.96) .860 (21.84) .880 (22.35) .024 (.61) .034 (.86) .068 (1.73) min .050 (1.27) bsc .150 (3.81) bsc .108 (2.74) ref pin 1 & 7 7 typ . pin 2 & 4 .040 (1.02) .060 (1.52) .190 (4.83) .210 (5.33) .012 (.30) .024 (.61) .080 (2.03) .120 (3.05) .234 (5.94) .261 (6.63) .165 (4.19) .185 (4.70) .040 (1.02) .060 (1.52) .045 (1.14) .055 (1.40) .670 (17.02) ref . .570 (14.48) ref . to-220-7c (y package)
rev. h 06/13 44 top252-262 www.powerint.com notes: 1. package dimensions conform to jedec speci?cation ms-001-ab (issue b 7/85) for standar d dual-in-line (dip) package with .300 inch r ow spacing. 2. contr olling dimensions ar e inches. millimeter sizes ar e shown in par entheses. 3. dimensions shown do not include mold ?ash or other pr otrusions. mold ?ash or pr otrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter -clock- wise to pin 8 when viewed fr om the top. the notch and/or dimple ar e aids in locating pin 1. pin 3 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measur ed at package body . 7. lead spacing measur ed with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 sea ting plane -d- -t - p08c pdip-8c (p package) pi-3933-040110 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum notes: 1. package dimensions conform to jedec speci?cation ms-019. 2. contr olling dimensions ar e inches. millimeter sizes ar e shown in par entheses. 3. dimensions shown do not include mold ?ash or other pr otrusions. mold ?ash or pr otrusions shall not exceed .006 (.15) on any side. 4. d, e and f ar e r efer ence datums. 5. dimensioning and tolerancing conform to asme y14.5m-1994. .008 (.20) .015 (.38) .300 (7.62) .390 (9.91) .240 (6.10) .260 (6.60) 10 6 15 .200 (5.08) max .020 (.51) min .367 (9.32) .387 (9.83) .120 (3.05) .140 (3.56) .030 (.76) .040 (1.02) .070 (1.78) bsc .300 bsc .300 (7.62) .340 (8.64 .014 (.36) .022 (.56) .125 (3.18) .145 (3.68) -e- sea ting plane -d- p10c sdip-10c (m package) pi-4648-101507 f d e .010 (.25) m -f-
rev. h 06/13 45 top252-262 www.powerint.com smd-8c (g package) pi-4015-101507 .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) .004 (.10) 0 - 8 .367 (9.32) .387 (9.83) .048 (1.22) .009 (.23) .053 (1.35) .032 (.81) .037 (.94) .125 (3.18) .145 (3.68) -d- notes: 1. contr olling dimensions ar e inches. millimeter sizes ar e shown in par entheses. 2. dimensions shown do not include mold ?ash or other pr otrusions. mold ?ash or pr otrusions shall not exceed .006 (.15) on any side. 3. pin locations start with pin 1, and continue counter -clock- wise to pin 8 when viewed fr om the top. pin 3 is omitted. 4. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 5. lead width measur ed at package body . 6. d and e ar e r efer enced datums on the package body . .057 (1.45) .068 (1.73) (note 5) e s .100 (2.54) (bsc) .372 (9.45) .240 (6.10) .388 (9.86) .260 (6.60) .010 (.25) -e- pin 1 d s .004 (.10) g08c .420 .046 .060 .060 .046 .080 pin 1 .086 .186 .286 solder pad dimensions .137 (3.48) minimum
rev. h 06/13 46 top252-262 www.powerint.com pi-4917-061510 mounting hole pattern (not to scale) pin 7 pin 1 0.100 (2.54) 0.100 (2.54) 0.059 (1.50) 0.059 (1.50) 0.050 (1.27) 0.050 (1.27) 0.100 (2.54) 0.155 (3.93) 0.020 (0.50) notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold ?ash, tie bar burrs, gate burrs, and interlead ?ash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead ?ash or protrusions. 5. controlling dimensions in inches (mm). 0.403 (10.24) 0.397 (10.08) 0.325 (8.25) 0.320 (8.13) 0.050 (1.27) front view 2 2 b a 0.070 (1.78) ref. pin #1 i.d. 3 c 0.016 (0.41) ref. 0.290 (7.37) ref. 0.047 (1.19) 0.100 (2.54) 0.519 (13.18) ref. 0.198 (5.04) ref. 0.264 (6.70) ref. 0.118 (3.00) 6 6 3 0.140 (3.56) 0.120 (3.05) 0.021 (0.53) 0.019 (0.48) 0.378 (9.60) ref. 0.019 (0.48) ref. 0.060 (1.52) ref. 0.048 (1.22) 0.046 (1.17) 0.081 (2.06) 0.077 (1.96) 0.207 (5.26) 0.187 (4.75) 0.033 (0.84) 0.028 (0.71) 0.016 (0.41) 0.011 (0.28) esip-7c (e package) 10 ref. all around 0.020 m 0.51 m c 0.010 m 0.25 m c a b side view end view back view 4 0.023 (0.58) 0.027 (0.70) detail a detail a
rev. h 06/13 47 top252-262 www.powerint.com 1 7 end view 0.021 (0.53) 0.019 (0.48) 0.060 (1.52) ref. 0.019 (0.48) ref. 0.378 (9.60) ref. 0.048 (1.22) 0.046 (1.17) c side view 6 0.129 (3.28) 0.122 (3.08) 0.081 (2.06) 0.077 (1.96) detail a 0.084 (2.14) 0.047 (1.19) ref. 0.290 (7.37) ref. 0.016 (0.41) 0.011 (0.28) 0.020 m 0.51 m c 3 pi-5204-061510 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold ?ash, tie bar burrs, gate burrs, and interlead ?ash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead ?ash or protrusions. 5. controlling dimensions in inches (mm). esip-7f (l package) 2 a b 1 7 bottom view pin 1 i.d. 0.403 (10.24) 0.397 (10.08) 0.325 (8.25) 0.320 (8.13) 0.050 (1.27) 0.070 (1.78) ref. exposed pad hidden exposed pad up 2 1 7 top view 0.089 (2.26) 0.079 (2.01) 0.173 (4.40) 0.163 (4.15) 0.198 (5.04) ref. 0.264 (6.70) ref. 0.100 (2.54) 0.490 (12.45) ref. 6 0.033 (0.84) 0.028 (0.71) 0.010 m 0.25 m c a b 4 3 0.020 (0.50) 0.023 (0.58) 0.027 (0.70) detail a (not drawn to scale)
rev. h 06/13 48 top252-262 www.powerint.com part ordering information ? topswitch product family ? hx series number ? package identifer p plastic dip-8c g plastic smd-8c m plastic sdip-10c y plastic to-220-7c e plastic esip-7c l plastic esip-7f ? pin finish n pure matte tin (pb-free) (p, g, m, e, l and y packages) g green mold compound (specifc e packages only) ? tape & reel and other options blank standard confgurations tl g package (1000 min/mult.) top 258 g n - tl
rev. h 06/13 49 top252-262 www.powerint.com revision notes date b data sheet release. 02/08 c added l package and top262. 07/08 d changed esip-7e to esip-7f. added detail to pi-4917 and pi-5204. 08/08 e released top255-259ln and top262en parts. 10/08 f added note for top256e halogen free part availability. 01/09 g added note for top258p and top259e halogen free part availability. updated e & l bend package drawings. minor text changes to page 27. 01/10 h added eg parts. removed note 7 from table 1 on page 2. 06/13
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, lytswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, hiperlcs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2013, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 1601/1610, tower 1, kerry everbright city no. 218 tianmu road west, shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) 3rd floor, block a, zhongtou international business center, no. 1061, xiang mei rd, futian district, shenzhen, china, 518040 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany lindwurmstrasse 114 80337 munich germany phone: +49-895-527-39110 fax: +49-895-527-39200 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via milanese 20, 3rd. fl. 20099 sesto san giovanni (mi) italy phone: +39-024-550-8701 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #19-01/05 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei 11493, taiwan r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760

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